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From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com,
	 alexandru.elisei@arm.com, suzuki.poulose@arm.com,
	mark.rutland@arm.com,  christoffer.dall@arm.com,
	pbonzini@redhat.com, drjones@redhat.com,  qperret@google.com,
	kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 kernel-team@android.com, tabba@google.com
Subject: [PATCH v3 08/15] KVM: arm64: Add feature register flag definitions
Date: Mon, 19 Jul 2021 17:03:39 +0100	[thread overview]
Message-ID: <20210719160346.609914-9-tabba@google.com> (raw)
In-Reply-To: <20210719160346.609914-1-tabba@google.com>

Add feature register flag definitions to clarify which features
might be supported.

Consolidate the various ID_AA64PFR0_ELx flags for all ELs.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/cpufeature.h |  4 ++--
 arch/arm64/include/asm/sysreg.h     | 12 ++++++++----
 arch/arm64/kernel/cpufeature.c      |  8 ++++----
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 9bb9d11750d7..b7d9bb17908d 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -602,14 +602,14 @@ static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
 {
 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
 
-	return val == ID_AA64PFR0_EL1_32BIT_64BIT;
+	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
 }
 
 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
 {
 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
 
-	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
+	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
 }
 
 static inline bool id_aa64pfr0_sve(u64 pfr0)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 326f49e7bd42..0b773037251c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -784,14 +784,13 @@
 #define ID_AA64PFR0_AMU			0x1
 #define ID_AA64PFR0_SVE			0x1
 #define ID_AA64PFR0_RAS_V1		0x1
+#define ID_AA64PFR0_RAS_ANY		0xf
 #define ID_AA64PFR0_FP_NI		0xf
 #define ID_AA64PFR0_FP_SUPPORTED	0x0
 #define ID_AA64PFR0_ASIMD_NI		0xf
 #define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
-#define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
-#define ID_AA64PFR0_EL1_32BIT_64BIT	0x2
-#define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
-#define ID_AA64PFR0_EL0_32BIT_64BIT	0x2
+#define ID_AA64PFR0_ELx_64BIT_ONLY	0x1
+#define ID_AA64PFR0_ELx_32BIT_64BIT	0x2
 
 /* id_aa64pfr1 */
 #define ID_AA64PFR1_MPAMFRAC_SHIFT	16
@@ -847,12 +846,16 @@
 #define ID_AA64MMFR0_ASID_SHIFT		4
 #define ID_AA64MMFR0_PARANGE_SHIFT	0
 
+#define ID_AA64MMFR0_ASID_8		0x0
+#define ID_AA64MMFR0_ASID_16		0x2
+
 #define ID_AA64MMFR0_TGRAN4_NI		0xf
 #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN64_NI		0xf
 #define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN16_NI		0x0
 #define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
+#define ID_AA64MMFR0_PARANGE_40		0x2
 #define ID_AA64MMFR0_PARANGE_48		0x5
 #define ID_AA64MMFR0_PARANGE_52		0x6
 
@@ -900,6 +903,7 @@
 #define ID_AA64MMFR2_CNP_SHIFT		0
 
 /* id_aa64dfr0 */
+#define ID_AA64DFR0_MTPMU_SHIFT		48
 #define ID_AA64DFR0_TRBE_SHIFT		44
 #define ID_AA64DFR0_TRACE_FILT_SHIFT	40
 #define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0ead8bfedf20..5b59fe5e26e4 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -239,8 +239,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
 	ARM64_FTR_END,
 };
 
@@ -1956,7 +1956,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sys_reg = SYS_ID_AA64PFR0_EL1,
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64PFR0_EL0_SHIFT,
-		.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
+		.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
 	},
 #ifdef CONFIG_KVM
 	{
@@ -1967,7 +1967,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sys_reg = SYS_ID_AA64PFR0_EL1,
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64PFR0_EL1_SHIFT,
-		.min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
+		.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
 	},
 	{
 		.desc = "Protected KVM",
-- 
2.32.0.402.g57bb445576-goog


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  parent reply	other threads:[~2021-07-19 16:14 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-19 16:03 [PATCH v3 00/15] KVM: arm64: Fixed features for protected VMs Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 01/15] KVM: arm64: placeholder to check if VM is protected Fuad Tabba
2021-08-12  8:58   ` Will Deacon
2021-08-12  9:22     ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 02/15] KVM: arm64: Remove trailing whitespace in comment Fuad Tabba
2021-08-12  8:59   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 03/15] KVM: arm64: MDCR_EL2 is a 64-bit register Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 04/15] KVM: arm64: Fix names of config register fields Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 05/15] KVM: arm64: Refactor sys_regs.h,c for nVHE reuse Fuad Tabba
2021-07-20 13:38   ` [PATCH v3 05/15] KVM: arm64: Refactor sys_regs.h, c " Andrew Jones
2021-07-20 14:03     ` Fuad Tabba
2021-08-12  8:59   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 06/15] KVM: arm64: Restore mdcr_el2 from vcpu Fuad Tabba
2021-07-20 14:52   ` Andrew Jones
2021-07-21  7:37     ` Fuad Tabba
2021-08-12  8:46       ` Will Deacon
2021-08-12  9:28         ` Fuad Tabba
2021-08-12  9:49           ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 07/15] KVM: arm64: Track value of cptr_el2 in struct kvm_vcpu_arch Fuad Tabba
2021-08-12  8:59   ` Will Deacon
2021-07-19 16:03 ` Fuad Tabba [this message]
2021-08-12  8:59   ` [PATCH v3 08/15] KVM: arm64: Add feature register flag definitions Will Deacon
2021-08-12  9:21     ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 09/15] KVM: arm64: Add config register bit definitions Fuad Tabba
2021-08-12  8:59   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 10/15] KVM: arm64: Guest exit handlers for nVHE hyp Fuad Tabba
2021-08-03 15:32   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 11/15] KVM: arm64: Add trap handlers for protected VMs Fuad Tabba
2021-08-12  9:45   ` Will Deacon
2021-08-16 14:39     ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 12/15] KVM: arm64: Move sanitized copies of CPU features Fuad Tabba
2021-08-12  9:46   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 13/15] KVM: arm64: Trap access to pVM restricted features Fuad Tabba
2021-08-12  9:53   ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 14/15] KVM: arm64: Handle protected guests at 32 bits Fuad Tabba
2021-07-19 19:43   ` Oliver Upton
2021-07-21  8:39     ` Fuad Tabba
2021-08-12  9:57   ` Will Deacon
2021-08-12 13:08     ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 15/15] KVM: arm64: Restrict protected VM capabilities Fuad Tabba
2021-08-12  9:59   ` Will Deacon
2021-08-16 14:40     ` Fuad Tabba

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