From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95E53C07E9B for ; Tue, 20 Jul 2021 20:45:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FBFA60FEA for ; Tue, 20 Jul 2021 20:45:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FBFA60FEA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=7h87IRwZTGVCBKyqSOMhN+JlXbQP1vso9qxaEC0KL7k=; b=340Rr9rHCIUSCQ rJbYU3XCNw9hldYOsum4h6G/HHS2TA96OZeFbm0gTRkdahCvx6ainqoZlG/VyPdnzxgmrd+DLR1w0 I4VMpKnzAWCOuXzth1WotVS2CzzLilUjmq7Y96Ey/imk7Z4T56kvHQG+VT6xRapvd/V/+v1t0iUGS io8j+it6rzEwzi5spY2cBxVQgBk+DrEwJTHhgHmjnX06GlNjx0dO4JpBDb/NXYX+XbsgCBJrxg39x pl84+6fSNjK7cdx2JgfDS/Alld26DDAEQbUPkRAMsuBomrVMGHr7qtAZRT9aH+MUS384payL3mjmz Tj2/tfPSUvieKLl9tffw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m5wav-00DuRq-Gt; Tue, 20 Jul 2021 20:44:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m5war-00DuRL-7F for linux-arm-kernel@lists.infradead.org; Tue, 20 Jul 2021 20:43:58 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 28BA360FF3; Tue, 20 Jul 2021 20:43:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626813836; bh=Fz8csP/TOy18/33qimKmRbshs6ScAXKv/l1vAHFMJjE=; h=From:To:Cc:Subject:Date:From; b=IyYchnmlkhh8nImFe/kDXDi/rQaD8LoTZnicCMgaDxQRk/lGLoQ9Tp/DPubrFp/jj 3npdXPSS7vuRK/IBK/qQWzT0jontOH5nI1G05acdClDXlFZMQIGnmIxMxc8fHZ0fnv h0qOOgCCPbsYmCK5WuWeUqtSFfVSyw6/7C+GCiGXQzeAkbcyUD+32RAUTWDUt5THor vG2usV+DnY+7fyceDzVmaBqbNzOgJYEhAI3kPc7sN1Kp4Xh5nZEKawja9E06/i5EzL NLNrMK3SRq4lSC3fSUiCAbYyRa+OhAlBfIojqbxDkcqHUhH1jvcJKs1ANVrv2PdZFV mS77rI5iL+Ivg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH] arm64/sme: Document boot requirements for SME Date: Tue, 20 Jul 2021 21:42:20 +0100 Message-Id: <20210720204220.22951-1-broonie@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1833; h=from:subject; bh=Fz8csP/TOy18/33qimKmRbshs6ScAXKv/l1vAHFMJjE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBg9scvdYYyqso6i/iRQkXkwpSARWm0GwxDk75vemEZ A668qeKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYPbHLwAKCRAk1otyXVSH0EaDCA CCzMabJdfRSEbxTo9i9fLrTmrUIvyUWBPVMZoA+Ah4FtoclTGZULchUB7YXVydnK+axEpRBJWP4jcH KZx5HbBEWoT5pSaKsMZ0/anz0qOWxYHaWSVtC4Mf/OxVpw7rGXAr+EhAYsv17phciWFDeh9+KiYo+y cv0uWzyR3YgI4NYDg4+aRUvZ7FwsMHPkrHjn9tUbL9h/fdQzJ1AlH6Ig02n1kNXMeffnelf84zglgV i8UjM4wyFv6reCWF/8A0g5Q+iW6JMA6ctp+Pc3Ydy/MMitCD8ESxLiTCJJnuX2BeDv0u0C6wzWgsnb ycoRUGhJzC5wb22h78OOsCzPAIYA1w X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210720_134357_323100_4D5FE39E X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document our requirements for initialisation of the Scalable Matrix Extension (SME) at kernel start. While we do have the ability to handle mismatched vector lengths we will reject any late CPUs that can't support the minimum set we determine at boot so for clarity we document a requirement that all CPUs make the same vector length available. Signed-off-by: Mark Brown --- Documentation/arm64/booting.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index a9192e7a231b..5822d6da9fa6 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -311,6 +311,28 @@ Before jumping into the kernel, the following conditions must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. + For CPUs with the Scalable Matrix Extension (FEAT_SME): + + - If EL3 is present: + + - CPTR_EL3.ESM (bit 12) must be initialised to 0b1. + + - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1. + + - SMCR_EL3.LEN must be initialised to the same value for all CPUs the + kernel will execute on. + + - If the kernel is entered at EL1 and EL2 is present: + + - CPTR_EL2.TSM (bit 12) must be initialised to 0b0. + + - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11. + + - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1. + + - SMCR_EL2.LEN must be initialised to the same value for all CPUs the + kernel will execute on. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel