Re: [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board

Shawn Guo
2021-07-23T06:31:37Z

On Wed, Jul 14, 2021 at 11:07:05PM +0200, Christoph Niedermaier wrote:
> The PDK2 board is capable of running both 100M and 1G ethernet. However,
> the i.MX6 has only one ethernet MAC, so it is possible to configure
> either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
> SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
> the PDK2 board with another RJ45 port. 100M and 1G ethernet use
> different signal pins from the i.MX6, but share the MDIO bus.
>
> This SoM board combination is used to demonstrate how to enable 1G
> ethernet configuration.
>
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Rebase on Shawn Guos branch for-next
> V3: - Rework of the commit message
> - Remove superfluous property max-speed
> V4: - No changes
> V5: - No changes
> V6: - Rebase on 5.14-rc1
> ---
> arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 51 ++++++++++++++++++++++++++++++++--
> 1 file changed, 48 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> index 4d455831b3ca..3b0276de41f9 100644
> --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> @@ -173,6 +173,46 @@
> status = "disabled";
> };
>
> +/* 1G ethernet */
> +/delete-node/ &ethphy0;
> +&fec {
> + phy-mode = "rgmii";
> + phy-handle = <&ethphy7>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet_1G>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy7: ethernet-phy@7 { /* KSZ 9021 */
> + compatible = "ethernet-phy-ieee802.3-c22";
> + interrupt-parent = <&gpio1>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-0 = <&pinctrl_ethphy7>;
> + pinctrl-names = "default";
> + reg = <7>;
> + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1000>;
> + reset-deassert-us = <1000>;
> +

Unnecessary newline in property list.

Shawn

> + rxc-skew-ps = <3000>;
> + rxd0-skew-ps = <0>;
> + rxd1-skew-ps = <0>;
> + rxd2-skew-ps = <0>;
> + rxd3-skew-ps = <0>;
> + txc-skew-ps = <3000>;
> + txd0-skew-ps = <0>;
> + txd1-skew-ps = <0>;
> + txd2-skew-ps = <0>;
> + txd3-skew-ps = <0>;
> + rxdv-skew-ps = <0>;
> + txen-skew-ps = <0>;
> + };
> + };
> +};
> +
> &hdmi {
> ddc-i2c-bus = <&i2c2>;
> status = "okay";
> @@ -255,9 +295,14 @@
> MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
> - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
> - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
> + >;
> + };
> +
> + pinctrl_ethphy7: ethphy7-grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
> + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
> >;
> };
>
> --
> 2.11.0
>