From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D395C4338F for ; Fri, 23 Jul 2021 06:42:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1C0460EE2 for ; Fri, 23 Jul 2021 06:42:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E1C0460EE2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u18NMx3R/p5EQXTOmnwUtC6n+I26voYrq6GuXcpSBkE=; b=DPNBmc24z45LVi sqSwMIbpWxbV3VIFN/lBXAfZrzPXYKQ4rBwPgRAOPrKY6RaLfeCFemwBKGGlvJFFfd+PzU5y5demU ANDHtidSKqnLlwoDhafrouE4oDsAWnOPRag48/J4RM/LQ5gtW5PnkHigaLCoafX1euJ494K1B1ITT W/CIw8feWwT10Lg+zvwiB+yhzWghIbd/t59qRt0lAu9Ba6LOJbgcwpg6sc3ImsnmN0p9X7OV+m8Bq UZNIh+EpKwWumsyCot/p/MzFskBWNHwj8QLC9ZJ07bdMPowvfGp65zkCnhhpOt2vTwHuT4lXZHr4S cZ9upSG2elNvgR3xDidQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6orK-003aNB-Gm; Fri, 23 Jul 2021 06:40:34 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6orF-003aMs-Mj for linux-arm-kernel@lists.infradead.org; Fri, 23 Jul 2021 06:40:31 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id D5E1160ED7; Fri, 23 Jul 2021 06:40:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627022429; bh=emCd4Sj25B29N2emi693jQztd4+o68AO2xgnh3CB2as=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pKOZNq5cpUmyTjdOdzjsgAT8Y4L+9AToPKbMSiwzpWVMzPYxd1LSGT7eNm0zg9r8k tbp/ievAhfVGFTZy/E7pmN0nLiDNoUWZWZ/vh9LmL9gEB9lTnRpuklxb7iXVLUk2eJ BIBcBgtgd1D8OwYSExMDhXHrOL/prbnVh3Krse/NWFRhXQmuDjrQsudp3FyN5+hs/S 6edflBeHbyV+f4WdjS9CHKbsAeVjwgjXC921sJWoRFjdBIdBytBnKn3CtqVGxHQ6Y6 guv9qmaPF8EtTeOoFEP7oz73zDH5+RDkb/NQ8+QdMPTENGPdn74UdDJU4M8v5YDBZv csXRdFr1MO4gA== Date: Fri, 23 Jul 2021 14:40:24 +0800 From: Shawn Guo To: Christoph Niedermaier Cc: linux-arm-kernel@lists.infradead.org, Fabio Estevam , Marek Vasut , NXP Linux Team , kernel@dh-electronics.com Subject: Re: [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls Message-ID: <20210723064022.GQ28658@dragon> References: <20210714210713.9015-1-cniedermaier@dh-electronics.com> <20210714210713.9015-8-cniedermaier@dh-electronics.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210714210713.9015-8-cniedermaier@dh-electronics.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210722_234029_829379_AE6F6E41 X-CRM114-Status: GOOD ( 23.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 14, 2021 at 11:07:06PM +0200, Christoph Niedermaier wrote: > Define each DHCOM GPIO as a separate pinctrl. So on board layer it is > possible to easily add an used DHCOM GPIO by moving &pinctrl_dhcom_X > from the gpio hog list to the appropriate driver pinctrl. I'm not sure this is a good idea. Each board should define the pinctrl for GPIO as per how it's used on the board. Shawn > > Signed-off-by: Christoph Niedermaier > Cc: Shawn Guo > Cc: Fabio Estevam > Cc: Marek Vasut > Cc: NXP Linux Team > Cc: kernel@dh-electronics.com > To: linux-arm-kernel@lists.infradead.org > --- > V2: - Rebase on Shawn Guos branch for-next > V3: - No changes > V4: - No changes > V5: - No changes > V6: - Rebase on 5.14-rc1 > --- > arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 105 ++++++++++++------------------- > arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 109 ++++++++++++++++++++++++++++++++- > 2 files changed, 148 insertions(+), 66 deletions(-) > > diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts > index 3b0276de41f9..8122db759880 100644 > --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts > +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts > @@ -38,7 +38,7 @@ > #size-cells = <0>; > interface-pix-fmt = "rgb24"; > pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_ipu1_lcdif>; > + pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; > status = "okay"; > > port@0 { > @@ -61,13 +61,13 @@ > gpio-keys { > #size-cells = <0>; > compatible = "gpio-keys"; > - pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_keys_pdk2>; > > button-0 { > label = "TA1-GPIO-A"; > linux,code = ; > gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; > + pinctrl-0 = <&pinctrl_dhcom_a>; > + pinctrl-names = "default"; > wakeup-source; > }; > > @@ -75,6 +75,8 @@ > label = "TA2-GPIO-B"; > linux,code = ; > gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; > + pinctrl-0 = <&pinctrl_dhcom_b>; > + pinctrl-names = "default"; > wakeup-source; > }; > > @@ -82,6 +84,8 @@ > label = "TA3-GPIO-C"; > linux,code = ; > gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; > + pinctrl-0 = <&pinctrl_dhcom_c>; > + pinctrl-names = "default"; > wakeup-source; > }; > > @@ -89,14 +93,14 @@ > label = "TA4-GPIO-D"; > linux,code = ; > gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; > + pinctrl-0 = <&pinctrl_dhcom_d>; > + pinctrl-names = "default"; > wakeup-source; > }; > }; > > led { > compatible = "gpio-leds"; > - pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_leds_pdk2>; > > /* > * Disable led-5, because GPIO E is > @@ -107,6 +111,8 @@ > function = LED_FUNCTION_INDICATOR; > gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ > default-state = "off"; > + pinctrl-0 = <&pinctrl_dhcom_e>; > + pinctrl-names = "default"; > status = "disabled"; > }; > > @@ -115,6 +121,8 @@ > function = LED_FUNCTION_INDICATOR; > gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ > default-state = "off"; > + pinctrl-0 = <&pinctrl_dhcom_f>; > + pinctrl-names = "default"; > }; > > led-7 { > @@ -122,6 +130,8 @@ > function = LED_FUNCTION_INDICATOR; > gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ > default-state = "off"; > + pinctrl-0 = <&pinctrl_dhcom_h>; > + pinctrl-names = "default"; > }; > > led-8 { > @@ -129,6 +139,8 @@ > function = LED_FUNCTION_INDICATOR; > gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ > default-state = "off"; > + pinctrl-0 = <&pinctrl_dhcom_i>; > + pinctrl-names = "default"; > }; > }; > > @@ -230,7 +242,7 @@ > > touchscreen@38 { > pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_touchscreen>; > + pinctrl-0 = <&pinctrl_dhcom_e>; > compatible = "edt,edt-ft5406"; > reg = <0x38>; > interrupt-parent = <&gpio4>; > @@ -240,34 +252,28 @@ > > &iomuxc { > pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>; > - > - pinctrl_hog: hog-grp { > - fsl,pins = < > - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0 > - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 > - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 > - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 > - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 > - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 > - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 > - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 > - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0 > - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0 > - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0 > - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0 > - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0 > - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0 > - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0 > - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0 > - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0 > - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0 > - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0 > - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0 > - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0 > - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0 > + pinctrl-0 = < > + /* > + * The following DHCOM GPIOs are used on this board. > + * Therefore, they have been removed from the list below. > + * A: key TA1 > + * B: key TA2 > + * C: key TA3 > + * D: key TA4 > + * E: touchscreen > + * F: led6 > + * G: backlight enable > + * H: led7 > + * I: led8 > + * J: PCIe reset > + */ > + &pinctrl_hog_base > + &pinctrl_dhcom_k &pinctrl_dhcom_l > + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o > + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r > + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u > + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int > >; > - }; > > pinctrl_audmux_ext: audmux-ext-grp { > fsl,pins = < > @@ -336,7 +342,6 @@ > MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 > MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 > MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 > - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 > >; > }; > > @@ -345,36 +350,6 @@ > MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 > >; > }; > - > - pinctrl_touchscreen: touchscreen-grp { > - fsl,pins = < > - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 > - >; > - }; > - > - pinctrl_pcie_reset: pcie-reset-grp { > - fsl,pins = < > - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x120b0 > - >; > - }; > - > - pinctrl_keys_pdk2: keys-pdk2-grp { > - fsl,pins = < > - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x120b0 /* TA1 */ > - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x120b0 /* TA2 */ > - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x120b0 /* TA3 */ > - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x120b0 /* TA4 */ > - >; > - }; > - > - pinctrl_leds_pdk2: leds-pdk2-grp { > - fsl,pins = < > - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x120b0 /* led6 */ > - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 /* led7 */ > - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x120b0 /* led8 */ > - >; > - }; > - > }; > > &ipu1_di0_disp0 { > @@ -382,7 +357,7 @@ > }; > > &pcie { > - pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>; > + pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; > reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; > status = "okay"; > }; > diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi > index c5c060c6b9bf..9fd48ab9b3d0 100644 > --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi > +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi > @@ -317,7 +317,17 @@ > > &iomuxc { > pinctrl-names = "default"; > - pinctrl-0 = <&pinctrl_hog_base>; > + pinctrl-0 = < > + &pinctrl_hog_base > + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c > + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f > + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i > + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l > + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o > + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r > + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u > + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int > + >; > > pinctrl_hog_base: hog-base-grp { > fsl,pins = < > @@ -329,6 +339,103 @@ > >; > }; > > + /* DHCOM GPIOs */ > + pinctrl_dhcom_a: dhcom-a-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_b: dhcom-b-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_c: dhcom-c-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_d: dhcom-d-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_e: dhcom-e-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_f: dhcom-f-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_g: dhcom-g-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_h: dhcom-h-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_i: dhcom-i-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_j: dhcom-j-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_k: dhcom-k-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_l: dhcom-l-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_m: dhcom-m-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_n: dhcom-n-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_o: dhcom-o-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_p: dhcom-p-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_q: dhcom-q-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_r: dhcom-r-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_s: dhcom-s-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_t: dhcom-t-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_u: dhcom-u-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_v: dhcom-v-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_w: dhcom-w-grp { > + fsl,pins = ; > + }; > + > + pinctrl_dhcom_int: dhcom-int-grp { > + fsl,pins = ; > + }; > + > pinctrl_ecspi1: ecspi1-grp { > fsl,pins = < > MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 > -- > 2.11.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel