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Wed, 28 Jul 2021 17:18:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m8nCD-001nt8-6P for linux-arm-kernel@lists.infradead.org; Wed, 28 Jul 2021 17:18:18 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0F56261038; Wed, 28 Jul 2021 17:18:14 +0000 (UTC) Date: Wed, 28 Jul 2021 18:18:12 +0100 From: Catalin Marinas To: Mark Rutland Cc: Peter Collingbourne , Vincenzo Frascino , Will Deacon , Andrey Konovalov , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit Message-ID: <20210728171811.GD7408@arm.com> References: <20210714013638.3995315-1-pcc@google.com> <20210714140442.GA28555@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210714140442.GA28555@C02TD0UTHF1T.local> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210728_101817_293416_9D9506F8 X-CRM114-Status: GOOD ( 13.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 14, 2021 at 03:04:42PM +0100, Mark Rutland wrote: > On Tue, Jul 13, 2021 at 06:36:38PM -0700, Peter Collingbourne wrote: > > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > > index ce59280355c5..2d6dc62d929a 100644 > > --- a/arch/arm64/kernel/entry.S > > +++ b/arch/arm64/kernel/entry.S > > @@ -175,15 +175,11 @@ alternative_else_nop_endif > > #endif > > .endm > > > > - .macro mte_set_gcr, tmp, tmp2 > > + .macro mte_set_gcr, mte_ctrl, tmp > > #ifdef CONFIG_ARM64_MTE > > - /* > > - * Calculate and set the exclude mask preserving > > - * the RRND (bit[16]) setting. > > - */ > > - mrs_s \tmp2, SYS_GCR_EL1 > > - bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 > > - msr_s SYS_GCR_EL1, \tmp2 > > + ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 > > + orr \tmp, \tmp, #SYS_GCR_EL1_RRND > > + msr_s SYS_GCR_EL1, \tmp > > #endif > > .endm > > Since the mte_ctrl value only has the Exclude bits set, we can make this > even simpler: > > orr \tmp, \mte_ctrl, #SYS_GCR_EL1_RRND > msr_s SYS_GCR_EL1, \tmp I don't think we can guarantee it following this patch (some other bits added to mte_ctrl): https://lore.kernel.org/r/20210727205300.2554659-3-pcc@google.com -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel