From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 388D0C4338F for ; Thu, 29 Jul 2021 15:27:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0334A60F22 for ; Thu, 29 Jul 2021 15:27:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0334A60F22 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QvO9uG/6fym1N5SGrTMdWSAbBfkRRSAJHCSOVvdTPhA=; b=gjDFAG2S86rML3 zsomY+8e67AkBhjJCgK3cT3owlRwYwltZadcaNwEbpDOreV7RdLnCVF5GcuWt+TICgJi061lIX+VQ P+XYLzDDV5s17q2Y+iRFKD2GG8I3O5nsU1TZgKjo7Gmsg7dHZChZWKiUzjRwqv1WeUJAcJ0DQD4iX KoZYSaF6csf/ycAsCXvj58Rq0SVoqUqSbLy2JhJi3DiTHvFA6psqE5sBW67poywPvJR2NsgfMUXt+ 4O1xrNStrurXgfMN+jPD7/uDdG/r0jUD3B1nL4PzNtUWIawz2rWHINjxdMMND2uern/+6tooFmbYD irSKDYFkWTXVyCrkw1sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m97tr-004hUe-Iq; Thu, 29 Jul 2021 15:24:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m97qH-004gYj-3N for linux-arm-kernel@lists.infradead.org; Thu, 29 Jul 2021 15:21:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 919621042; Thu, 29 Jul 2021 08:21:00 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C57913F73D; Thu, 29 Jul 2021 08:20:59 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: Andre.Przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com, Wei.Chen@arm.com Subject: [boot-wrapper PATCH 03/12] Remove cache maintenance Date: Thu, 29 Jul 2021 16:20:41 +0100 Message-Id: <20210729152050.23635-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210729152050.23635-1-mark.rutland@arm.com> References: <20210729152050.23635-1-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_082101_309418_30FEC919 X-CRM114-Status: GOOD ( 16.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For models, we assume that out-of-reset caches ar invalid and no cache maintenance is required. We added cache maintenance to the boot-wrapper in commit: 28ec269a22c8dc14 ("Add code to clean and invalidate caches") ... because the boot-wrapper would teansiently use cacheable mappings, and could allocate into caches. As we were using Set/Way operations, we were on somewhat shaky ground (e.g. due to system-level caches, or dirty line migration). Further, we never took FEAT_CCIDX into account, and so would not necessarily invalidate all potential levels of cache However, since commit: 0bb7b2545582accf ("Remove MMU identity map setup") ... we no longer enable the MMU within the boot-wrapper, and so no longer have any reason to perform cache maintenance. This patch removes the redundant and incomplete cache maintenance. Signed-off-by: Mark Rutland --- Makefile.am | 2 +- boot_common.c | 3 --- cache.c | 58 ---------------------------------------------------------- 3 files changed, 1 insertion(+), 62 deletions(-) delete mode 100644 cache.c diff --git a/Makefile.am b/Makefile.am index ef6b793..8334049 100644 --- a/Makefile.am +++ b/Makefile.am @@ -123,7 +123,7 @@ CFLAGS += -Wall -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections LDFLAGS += --gc-sections -OFILES += boot_common.o bakery_lock.o platform.o $(GIC) cache.o lib.o +OFILES += boot_common.o bakery_lock.o platform.o $(GIC) lib.o OFILES += $(addprefix $(ARCH_SRC),boot.o stack.o $(BOOTMETHOD) utils.o) # Don't lookup all prerequisites in $(top_srcdir), only the source files. When diff --git a/boot_common.c b/boot_common.c index e7b8e1d..d48b7e1 100644 --- a/boot_common.c +++ b/boot_common.c @@ -13,7 +13,6 @@ extern unsigned long entrypoint; extern unsigned long dtb; void init_platform(void); -void flush_caches(void); void __noreturn jump_kernel(unsigned long address, unsigned long a0, @@ -62,8 +61,6 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry) void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid) { - flush_caches(); - if (cpu == 0) { init_platform(); diff --git a/cache.c b/cache.c deleted file mode 100644 index 9d71248..0000000 --- a/cache.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * cache.c - simple cache clean+invalidate code - * - * Copyright (C) 2015 ARM Limited. All rights reserved. - * - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE.txt file. - */ - -#include - -void flush_caches(void) -{ - unsigned int level; - uint32_t clidr = read_clidr(); - unsigned int max_level = (clidr >> 24) & 0x7; - - uint32_t ccsidr; - - if (max_level == 0) - return; - - for (level = 0; level < max_level; level++) { - uint32_t cache_type = (clidr >> (level * 3)) & 0x7; - unsigned int line_size, num_ways, num_sets, way_shift; - unsigned int way, set; - - if (cache_type == 1) - /* No dcache at this level */ - continue; - - write_csselr(level << 1); - isb(); - ccsidr = read_ccsidr(); - - line_size = (ccsidr & 0x7) + 4; /* log2 line size */ - num_ways = ((ccsidr >> 3) & 0x3ff) + 1; - num_sets = ((ccsidr >> 13) & 0x7fff) + 1; - - way_shift = clz(num_ways - 1); - for (way = 0; way < num_ways; way++) { - for (set = 0; set < num_sets; set++) { - uint32_t command = level << 1; - command |= way << way_shift; - command |= set << line_size; - - dccisw(command); - dsb(sy); - } - } - - dsb(sy); - } - dsb(sy); - iciallu(); - dsb(sy); - isb(); -} -- 2.11.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel