From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 417DEC432BE for ; Mon, 9 Aug 2021 17:42:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF36C60F56 for ; Mon, 9 Aug 2021 17:42:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DF36C60F56 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xyp3zB6Xtfk8+hE5qghu3/vUXE4iKazG54l07PXCf8Y=; b=mm7f1iN+hwy3we JwqgcUi5fqlJBQQcC6772QdMaP2ryF6rqJRMZsLCxgyaHsgfPzNvLeInv/JSuZTEhjuZpqEEjCz7y tDHiyfq1DiAi+F0DG9YSMEHkbEyIxyK1O4uAN5+mM7eXN3plFXrjPbDQriMZXBsO+SrQApniCrI18 m+BuXyTOb6GT2VEgZVeU9DLscFws2/ASgs+m7xPPa+0xBi6zaAvq09jZlHEidfvPdI51E1OQT7Eo+ MUNcLCx0pdQM19CUwy/CqmeCikwbVGZ46EeVr7J4u6CuTDZewRzHCg0OaeMjsVZwdomhmWunLbbl+ /WIakLCyRnLhc839Bp8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD9GM-001a92-1c; Mon, 09 Aug 2021 17:40:34 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD9GH-001a8g-JY for linux-arm-kernel@lists.infradead.org; Mon, 09 Aug 2021 17:40:31 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6D5C56056B; Mon, 9 Aug 2021 17:40:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1628530829; bh=BIKbIviH9SpdRUOz4zp7Qr9LpfMy8guxskktS3QxA2c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YxJy11mivVEo2UaBSB2xiRgRmjERNhE4SAb9XXON7MqwSwaegBla8YhtlQ0M97H/v ddzB4KQPMUy8eR4Nb+Ylch/pCyZbDfeE3tGaPChCILwJK/2q0RRkhNYQkbcGH70re0 9Jwq1wnQL+fAiRQ1GbJvQoxnvA+jTbbqC/Nd4gK2Qhesw5nRwk5NMHprVCI7KuITvJ iDnF0DF25umEYeh0IQv92pi7+OWU3t4wP1GICbH63L7+b7XS1hwOThYj7eGVchmdYo uHA2MZxJs2VNT6mQ+E1jMEQXw4pTXfYdIvhUYkqHYqBPjE2DyaXcU/E23ebgOtBlwh 7X7g2G6tevPug== Date: Mon, 9 Aug 2021 18:40:23 +0100 From: Will Deacon To: Rob Clark Cc: Sai Prakash Ranjan , Georgi Djakov , "Isaac J. Manjarres" , David Airlie , Akhil P Oommen , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Linux Kernel Mailing List , Sean Paul , Jordan Crouse , Kristian H Kristensen , dri-devel , Daniel Vetter , linux-arm-msm , freedreno , Robin Murphy , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Subject: Re: [Freedreno] [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Message-ID: <20210809174022.GA1840@willie-the-truck> References: <20210728140052.GB22887@mms-0441> <8b2742c8891abe4fec3664730717a089@codeaurora.org> <20210802105544.GA27657@willie-the-truck> <20210802151409.GE28735@willie-the-truck> <20210809145651.GC1458@willie-the-truck> <20210809170508.GB1589@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210809_104029_728780_5FF7AE1A X-CRM114-Status: GOOD ( 53.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 09, 2021 at 10:18:21AM -0700, Rob Clark wrote: > On Mon, Aug 9, 2021 at 10:05 AM Will Deacon wrote: > > > > On Mon, Aug 09, 2021 at 09:57:08AM -0700, Rob Clark wrote: > > > On Mon, Aug 9, 2021 at 7:56 AM Will Deacon wrote: > > > > On Mon, Aug 02, 2021 at 06:36:04PM -0700, Rob Clark wrote: > > > > > On Mon, Aug 2, 2021 at 8:14 AM Will Deacon wrote: > > > > > > On Mon, Aug 02, 2021 at 08:08:07AM -0700, Rob Clark wrote: > > > > > > > On Mon, Aug 2, 2021 at 3:55 AM Will Deacon wrote: > > > > > > > > On Thu, Jul 29, 2021 at 10:08:22AM +0530, Sai Prakash Ranjan wrote: > > > > > > > > > On 2021-07-28 19:30, Georgi Djakov wrote: > > > > > > > > > > On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > > > > > > > > > > > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > > > > > > > > > > > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > > > > > > > > > > > the memory type setting required for the non-coherent masters to use > > > > > > > > > > > system cache. Now that system cache support for GPU is added, we will > > > > > > > > > > > need to set the right PTE attribute for GPU buffers to be sys cached. > > > > > > > > > > > Without this, the system cache lines are not allocated for GPU. > > > > > > > > > > > > > > > > > > > > > > So the patches in this series introduces a new prot flag IOMMU_LLC, > > > > > > > > > > > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > > > > > > > > > > > and makes GPU the user of this protection flag. > > > > > > > > > > > > > > > > > > > > Thank you for the patchset! Are you planning to refresh it, as it does > > > > > > > > > > not apply anymore? > > > > > > > > > > > > > > > > > > > > > > > > > > > > I was waiting on Will's reply [1]. If there are no changes needed, then > > > > > > > > > I can repost the patch. > > > > > > > > > > > > > > > > I still think you need to handle the mismatched alias, no? You're adding > > > > > > > > a new memory type to the SMMU which doesn't exist on the CPU side. That > > > > > > > > can't be right. > > > > > > > > > > > > > > > > > > > > > > Just curious, and maybe this is a dumb question, but what is your > > > > > > > concern about mismatched aliases? I mean the cache hierarchy on the > > > > > > > GPU device side (anything beyond the LLC) is pretty different and > > > > > > > doesn't really care about the smmu pgtable attributes.. > > > > > > > > > > > > If the CPU accesses a shared buffer with different attributes to those which > > > > > > the device is using then you fall into the "mismatched memory attributes" > > > > > > part of the Arm architecture. It's reasonably unforgiving (you should go and > > > > > > read it) and in some cases can apply to speculative accesses as well, but > > > > > > the end result is typically loss of coherency. > > > > > > > > > > Ok, I might have a few other sections to read first to decipher the > > > > > terminology.. > > > > > > > > > > But my understanding of LLC is that it looks just like system memory > > > > > to the CPU and GPU (I think that would make it "the point of > > > > > coherence" between the GPU and CPU?) If that is true, shouldn't it be > > > > > invisible from the point of view of different CPU mapping options? > > > > > > > > You could certainly build a system where mismatched attributes don't cause > > > > loss of coherence, but as it's not guaranteed by the architecture and the > > > > changes proposed here affect APIs which are exposed across SoCs, then I > > > > don't think it helps much. > > > > > > > > > > Hmm, the description of the new mapping flag is that it applies only > > > to transparent outer level cache: > > > > > > +/* > > > + * Non-coherent masters can use this page protection flag to set cacheable > > > + * memory attributes for only a transparent outer level of cache, also known as > > > + * the last-level or system cache. > > > + */ > > > +#define IOMMU_LLC (1 << 6) > > > > > > But I suppose we could call it instead IOMMU_QCOM_LLC or something > > > like that to make it more clear that it is not necessarily something > > > that would work with a different outer level cache implementation? > > > > ... or we could just deal with the problem so that other people can reuse > > the code. I haven't really understood the reluctance to solve this properly. > > > > Am I missing some reason this isn't solvable? > > Oh, was there another way to solve it (other than foregoing setting > INC_OCACHE in the pgtables)? Maybe I misunderstood, is there a > corresponding setting on the MMU pgtables side of things? Right -- we just need to program the CPU's MMU with the matching memory attributes! It's a bit more fiddly if you're just using ioremap_wc() though, as it's usually the DMA API which handles the attributes under the hood. Anyway, sorry, I should've said that explicitly earlier on. We've done this sort of thing in the Android tree so I assumed Sai knew what needed to be done and then I didn't think to explain to you :( Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel