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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id y13sm3250995pjr.1.2021.09.21.10.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 10:24:41 -0700 (PDT) Date: Tue, 21 Sep 2021 11:24:39 -0600 From: Mathieu Poirier To: Suzuki K Poulose Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, tamas.zsoldos@arm.com, jinlmao@qti.qualcomm.com, al.grant@arm.com, denik@google.com Subject: Re: [PATCH v3 06/10] coresight: trbe: Fix handling of spurious interrupts Message-ID: <20210921172439.GC2059841@p14s> References: <20210914102641.1852544-1-suzuki.poulose@arm.com> <20210914102641.1852544-7-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210914102641.1852544-7-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_102444_364479_B7D60C4D X-CRM114-Status: GOOD ( 28.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 14, 2021 at 11:26:37AM +0100, Suzuki K Poulose wrote: > On a spurious IRQ, right now we disable the TRBE and then re-enable > it back, resetting the "buffer" pointers(i.e BASE, LIMIT and more > importantly WRITE) to the original pointers from the AUX handle. > This implies that we overwrite any trace that was written so far, > (by overwriting TRBPTR) while we should have ignored the IRQ. > > This patch cleans the behavior, by only stopping the TRBE if the > IRQ was indeed raised, as we can read the TRBSR without stopping > the TRBE (Only writes to the TRBSR requires the TRBE disabled). > And also, on detecting a spurious IRQ after examining the TRBSR, > we simply re-enable the TRBE without touching the other parameters. > > Cc: Anshuman Khandual > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Leo Yan > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-trbe.c | 30 ++++++++++---------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 5297b11f26b7..de99dd0aecd3 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -677,16 +677,16 @@ static int arm_trbe_disable(struct coresight_device *csdev) > > static void trbe_handle_spurious(struct perf_output_handle *handle) > { > - struct trbe_buf *buf = etm_perf_sink_config(handle); > + u64 limitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > - buf->trbe_limit = compute_trbe_buffer_limit(handle); > - buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf); > - if (buf->trbe_limit == buf->trbe_base) { > - trbe_drain_and_disable_local(); > - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); > - return; > - } > - trbe_enable_hw(buf); > + /* > + * If the IRQ was spurious, simply re-enable the TRBE > + * back without modifying the buffer parameters to > + * retain the trace collected so far. > + */ > + limitr |= TRBLIMITR_ENABLE; > + write_sysreg_s(limitr, SYS_TRBLIMITR_EL1); > + isb(); I understand (and agree with) this part of the patch... > } > > static void trbe_handle_overflow(struct perf_output_handle *handle) > @@ -759,12 +759,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > enum trbe_fault_action act; > u64 status; > > - /* > - * Ensure the trace is visible to the CPUs and > - * any external aborts have been resolved. > - */ > - trbe_drain_and_disable_local(); > - > + /* Reads to TRBSR_EL1 is fine when TRBE is active */ > status = read_sysreg_s(SYS_TRBSR_EL1); > /* > * If the pending IRQ was handled by update_buffer callback > @@ -773,6 +768,11 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > if (!is_trbe_irq(status)) > return IRQ_NONE; > > + /* > + * Ensure the trace is visible to the CPUs and > + * any external aborts have been resolved. > + */ > + trbe_drain_and_disable_local(); But not this part... I can see why you'd want to move this after the check for is_trbe_irq(), but not how it relates to spurious interrupts. To me it seems like it is addressing another issue. If those code snippets are related then a good dose of comments is missing. Thanks, Mathieu > clr_trbe_irq(); > isb(); > > -- > 2.24.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel