From: Lucas Stach <l.stach@pengutronix.de>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Adam Ford <aford173@gmail.com>,
Frieder Schrempf <frieder.schrempf@kontron.de>,
Marek Vasut <marex@denx.de>, Tim Harvey <tharvey@gateworks.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: [PATCH v5 14/18] arm64: dts: imx8mm: add GPC node
Date: Sat, 2 Oct 2021 02:59:50 +0200 [thread overview]
Message-ID: <20211002005954.1367653-15-l.stach@pengutronix.de> (raw)
In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de>
Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 2f632e8ca388..83185b70dd46 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -7,6 +7,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mm-pinfunc.h"
@@ -610,6 +612,111 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MM_CLK_USB_BUS>;
+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+ };
+
+ pgc_pcie: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+ power-domains = <&pgc_hsiomix>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+ };
+
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_OTG1>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_OTG2>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_gpumix: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
+ clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MM_CLK_GPU_AHB>;
+ assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
+ <&clk IMX8MM_CLK_GPU_AHB>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+ <&clk IMX8MM_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>, <400000000>;
+ };
+
+ pgc_gpu: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_GPU>;
+ clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MM_CLK_GPU2D_ROOT>,
+ <&clk IMX8MM_CLK_GPU3D_ROOT>;
+ resets = <&src IMX8MQ_RESET_GPU_RESET>;
+ power-domains = <&pgc_gpumix>;
+ };
+
+ pgc_vpumix: power-domain@6 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
+ clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
+ resets = <&src IMX8MQ_RESET_VPU_RESET>;
+ };
+
+ pgc_vpu_g1: power-domain@7 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
+ };
+
+ pgc_vpu_g2: power-domain@8 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
+ };
+
+ pgc_vpu_h1: power-domain@9 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
+ };
+
+ pgc_dispmix: power-domain@10 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+ assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
+ <&clk IMX8MM_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+ <&clk IMX8MM_SYS_PLL1_800M>;
+ assigned-clock-rates = <500000000>, <200000000>;
+ };
+
+ pgc_mipi: power-domain@11 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
--
2.30.2
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next prev parent reply other threads:[~2021-10-02 1:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-02 0:59 [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Lucas Stach
2021-10-02 0:59 ` [PATCH v5 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Lucas Stach
2021-10-03 10:43 ` Adam Ford
2021-10-03 19:46 ` Lucas Stach
2021-10-04 0:03 ` Adam Ford
2021-10-02 0:59 ` [PATCH v5 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield Lucas Stach
2021-10-02 0:59 ` [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Lucas Stach
2021-10-02 0:59 ` [PATCH v5 04/18] soc: imx: gpcv2: add lockdep annotation Lucas Stach
2021-10-02 0:59 ` [PATCH v5 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Lucas Stach
2021-10-02 0:59 ` [PATCH v5 06/18] soc: imx: gpcv2: keep i.MX8M* bus " Lucas Stach
2021-10-02 0:59 ` [PATCH v5 07/18] soc: imx: gpcv2: support system suspend/resume Lucas Stach
2021-12-08 13:47 ` [PATCH] hack: soc: imx: gpcv2: avoid unbalanced powering off of one device Martin Kepplinger
2021-12-08 14:05 ` Lucas Stach
2021-12-22 8:12 ` Martin Kepplinger
2021-10-02 0:59 ` [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Lucas Stach
2021-10-02 0:59 ` [PATCH v5 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Lucas Stach
2021-10-02 0:59 ` [PATCH v5 10/18] soc: imx: add i.MX8M blk-ctrl driver Lucas Stach
2021-10-02 0:59 ` [PATCH v5 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Lucas Stach
2021-10-02 0:59 ` [PATCH v5 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Lucas Stach
2021-10-02 0:59 ` [PATCH v5 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Lucas Stach
2021-10-02 0:59 ` Lucas Stach [this message]
2021-10-02 0:59 ` [PATCH v5 15/18] arm64: dts: imx8mm: put USB controllers into power-domains Lucas Stach
2021-10-02 0:59 ` [PATCH v5 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Lucas Stach
2021-10-02 0:59 ` [PATCH v5 17/18] arm64: dts: imx8mm: add VPU blk-ctrl Lucas Stach
2021-10-02 0:59 ` [PATCH v5 18/18] arm64: dts: imx8mm: add DISP blk-ctrl Lucas Stach
2021-10-05 6:40 ` [PATCH v5 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Shawn Guo
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