From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, will@kernel.org,
catalin.marinas@arm.com, mathieu.poirier@linaro.org,
mike.leach@linaro.org, leo.yan@linaro.org,
anshuman.khandual@arm.com, coresight@lists.linaro.org,
maz@kernel.org, james.morse@arm.com, mark.rutland@arm.com,
lcherian@marvell.com, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 01/16] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
Date: Fri, 8 Oct 2021 19:28:51 +0100 [thread overview]
Message-ID: <20211008182906.1688009-2-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211008182906.1688009-1-suzuki.poulose@arm.com>
Add the CPU Partnumbers for the new Arm designs.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/cputype.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 6231e1f0abe7..19b8441aa8f2 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,8 @@
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
+#define ARM_CPU_PART_CORTEX_A710 0xD47
+#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define APM_CPU_PART_POTENZA 0x000
@@ -113,6 +115,8 @@
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
+#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.25.4
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next prev parent reply other threads:[~2021-10-08 18:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 18:28 [PATCH v3 00/16] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-08 18:28 ` Suzuki K Poulose [this message]
2021-10-08 18:28 ` [PATCH v3 02/16] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 03/16] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-11 10:20 ` Will Deacon
2021-10-08 18:28 ` [PATCH v3 04/16] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 05/16] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 06/16] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 07/16] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 08/16] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 09/16] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 10/16] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 11/16] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 12/16] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 13/16] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 14/16] arm64: errata: Advertise workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures Suzuki K Poulose
2021-10-11 10:18 ` Will Deacon
2021-10-11 12:32 ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 16/16] arm64: errata: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
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