From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 868B6C433F5 for ; Sun, 10 Oct 2021 11:45:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C1A2610CE for ; Sun, 10 Oct 2021 11:45:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4C1A2610CE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=wOTmg2zR47BJ4oe8VzHcLes3nyc5pWtqzRzXheu5uHI=; b=rJxmLdHSBuzAQa ksfhRNg6MI6fqg4O1KXbEucPk1SeqhOAmlUjCFdzV7/j5uTkcTMnOtH+vtZZ0TkaaVkjOjT9+l5SI /oUqpABuaCXdAtdV26+0usBV9iS5hG8dgxQRZ1bM5XaeX8HXywnaeOL0K8VshTXwsDJj1tS7zb1rk uYJQYtUxbxgO6L50dhwj5eahMEO53CqkPbFEevWpHAUSWWxPm8tJ4+5DQ0s8u1uqASldTJhsd2z9f CVg4m4UkXha2jGT5j4OKjP7vvlk9PX/T1kbamrYSkxDcAJNFBqdztrqdY5oS0HEDtbdJdXKI9ccaM Y4GXo5YwlTlbLGOWrtUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZXEl-006fa4-S5; Sun, 10 Oct 2021 11:43:28 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZXEW-006fUL-O1 for linux-arm-kernel@lists.infradead.org; Sun, 10 Oct 2021 11:43:14 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 29D4F610CF; Sun, 10 Oct 2021 11:43:12 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mZXET-00FqFc-QT; Sun, 10 Oct 2021 12:43:10 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton , Will Deacon , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Date: Sun, 10 Oct 2021 12:42:49 +0100 Message-Id: <20211010114306.2910453-1-maz@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, pshier@google.com, rananta@google.com, ricarkol@google.com, oupton@google.com, will@kernel.org, catalin.marinas@arm.com, linus.walleij@linaro.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211010_044312_862361_329954E5 X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is v3 of the series enabling ARMv8.6 support for timer subsystem, and was prompted by a discussion with Oliver around the fact that an ARMv8.6 implementation must have a 1GHz counter, which leads to a number of things to break in the timer code: - the counter rollover can come pretty quickly as we only advertise a 56bit counter, - the maximum timer delta can be remarkably small, as we use the countdown interface which is limited to 32bit... Thankfully, there is a way out: we can compute the minimal width of the counter based on the guarantees that the architecture gives us, and we can use the 64bit comparator interface instead of the countdown to program the timer. Finally, we start making use of the ARMv8.6 ECV features by switching accesses to the counters to a self-synchronising register, removing the need for an ISB. Hopefully, implementations will *not* just stick an invisible ISB there... A side effect of the switch to CVAL is that XGene-1 breaks. I have added a workaround to keep it alive. I have added Oliver's original patch[0] to the series and tweaked a couple of things. Blame me if I broke anything. The whole things has been tested on Juno (sysreg + MMIO timers), XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0). * From v2 [2]: - New patch adding a HWCAP (ECV) allowing userspace to probe for the presence of CNTVSS_EL0. * From v1 [1]: - New patch adding a bunch of BUILD_BUG()s for register accesses we don't expect. This makes subsequent patches much simpler. - New patch moving the ISBs for workaround in a way that makes more sense for the self-synchronising accessors. - Rework the XGene-1 workaround to rely solely on MIDR. - Split the CNTVCTSS trap handling in its own patch. - Rebased on 5.15-rc2 - Collected RBs, with thanks. [0] https://lore.kernel.org/r/20210807191428.3488948-1-oupton@google.com [1] https://lore.kernel.org/r/20210809152651.2297337-2-maz@kernel.org [2] https://lore.kernel.org/r/20210922211941.2756270-1-maz@kernel.org Marc Zyngier (16): clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 clocksource/arm_arch_timer: Move system register timer programming over to CVAL clocksource/arm_arch_timer: Move drop _tval from erratum function names clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL clocksource/arm_arch_timer: Advertise 56bit timer to the core code clocksource/arm_arch_timer: Work around broken CVAL implementations clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming clocksource/arch_arm_timer: Move workaround synchronisation around arm64: Add a capability for FEAT_ECV arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 arm64: Add handling of CNTVCTSS traps arm64: Add HWCAP for self-synchronising virtual counter Oliver Upton (1): clocksource/arm_arch_timer: Fix masking for high freq counters Documentation/arm64/elf_hwcaps.rst | 4 + arch/arm/include/asm/arch_timer.h | 37 ++-- arch/arm64/include/asm/arch_timer.h | 78 +++++---- arch/arm64/include/asm/esr.h | 6 + arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/asm/sysreg.h | 3 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 13 +- arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/traps.c | 11 ++ arch/arm64/tools/cpucaps | 1 + drivers/clocksource/arm_arch_timer.c | 243 ++++++++++++++++----------- include/clocksource/arm_arch_timer.h | 2 +- 13 files changed, 254 insertions(+), 147 deletions(-) -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel