From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B984CC433F5 for ; Mon, 11 Oct 2021 11:01:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 81D8360EDF for ; Mon, 11 Oct 2021 11:01:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 81D8360EDF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qDf8Z1zYSax87XmSzDn0VkpJjNJkYleVaZb5wqS2I5w=; b=EXhGSz5tF/AsO6 5KigaJdfCNHL6PbjLpoK5fsES08aqGaAcKgj99Mcm82HtBSyTL1TDWJa+Txxc06DtwkbdHwK2rBtm K3PdbY3nOi+w04S2D3tNHn+3bkWAp4cDU9/kRjVM1eVV8KhIxkVxfZdJe7KVER9dxbL7mkMsB8NmW LQl2hLd0dmAuBJjKEZenljGzMXcMASH5k+XYBzsfdbbsijs0x6tPVaOKyqvmdXdpBAc6f6w0LQI9o Q2VicxWc/TxA0wh3G9MXh+/qe8XyYMQmujxzvoOJ9p8aGd/Mxi4Zpyi23rpzaUTQOT1yGIvkiWRgB LqILjt2+OilPBO04rdRg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZt2Z-008xci-3o; Mon, 11 Oct 2021 11:00:19 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZt2U-008xbT-VM for linux-arm-kernel@lists.infradead.org; Mon, 11 Oct 2021 11:00:16 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 72D4360EB4; Mon, 11 Oct 2021 11:00:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633950014; bh=vQIFuyPINjrBi0fIpVIivAP7Ib5rZs4uIJ6rAcpaTwQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NDqTb4Z1xe9+3UDiejqPqrsL04x+glEXFzdE7lgx1II8LiLA6PyJAjVinBCee/tWF Tb/0dn4/0yDEsO1vlnorgpxAJHaJOqWZDiHRbiaNZx3Lh3UsIHcCj51AfH9Yyg1vIf dSNplmLI6C2ziwrQZHTWQHdipz6SjMe5G94+MHbRkHuW1L8g8LdIewkhFJahS5Jnoh 0Q6zvkWfJ/iLK1XOlEllbcwk2NKjpVTxOjuH8syvN3GMaYp5R6Yiv5h7C7YwRN3ye5 6MSaC4iJj683V0JFcQnWbId7JcrdTv8OFabmeORKE63JDBewPdPxdnzkYchw7oyU7W gbSRyJiBfpNyg== Date: Mon, 11 Oct 2021 12:00:09 +0100 From: Will Deacon To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: Re: [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter Message-ID: <20211011110008.GA4068@willie-the-truck> References: <20211010114306.2910453-1-maz@kernel.org> <20211010114306.2910453-18-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211010114306.2910453-18-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211011_040015_074874_99D3A9F2 X-CRM114-Status: GOOD ( 18.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Oct 10, 2021 at 12:43:06PM +0100, Marc Zyngier wrote: > Since userspace can make use of the CNTVSS_EL0 instruction, expose > it via a HWCAP. > > Suggested-by: Will Deacon > Signed-off-by: Marc Zyngier > --- > Documentation/arm64/elf_hwcaps.rst | 4 ++++ > arch/arm64/include/asm/hwcap.h | 1 + > arch/arm64/include/uapi/asm/hwcap.h | 1 + > arch/arm64/kernel/cpufeature.c | 3 ++- > arch/arm64/kernel/cpuinfo.c | 1 + > 5 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst > index ec1a5a63c1d0..af106af8e1c0 100644 > --- a/Documentation/arm64/elf_hwcaps.rst > +++ b/Documentation/arm64/elf_hwcaps.rst > @@ -247,6 +247,10 @@ HWCAP2_MTE > Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described > by Documentation/arm64/memory-tagging-extension.rst. > > +HWCAP2_ECV > + > + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. > + > 4. Unused AT_HWCAP bits > ----------------------- > > diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h > index 8c129db8232a..b100e0055eab 100644 > --- a/arch/arm64/include/asm/hwcap.h > +++ b/arch/arm64/include/asm/hwcap.h > @@ -105,6 +105,7 @@ > #define KERNEL_HWCAP_RNG __khwcap2_feature(RNG) > #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI) > #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) > +#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) > > /* > * This yields a mask that user programs can use to figure out what > diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h > index b8f41aa234ee..7b23b16f21ce 100644 > --- a/arch/arm64/include/uapi/asm/hwcap.h > +++ b/arch/arm64/include/uapi/asm/hwcap.h > @@ -75,5 +75,6 @@ > #define HWCAP2_RNG (1 << 16) > #define HWCAP2_BTI (1 << 17) > #define HWCAP2_MTE (1 << 18) > +#define HWCAP2_ECV (1 << 19) > > #endif /* _UAPI__ASM_HWCAP_H */ > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 26b11ce8fff6..97ed37c6ce5e 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), This needs an update to Documentation/arm64/cpu-feature-registers.rst. With that: Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel