From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C13FC433F5 for ; Tue, 12 Oct 2021 14:43:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAEBA60F23 for ; Tue, 12 Oct 2021 14:43:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DAEBA60F23 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pan+yJ4nPXMnogmr7ed2Kj+4jH/nmHtEBDvKKfUg4Ac=; b=AUuxMASFoG6FkA ItcUJDUn0RHOKHHlM3GHlHmxeQzTRHOz80lEkBvhIt7wFvDt6oM5+bRfV9gCfCA+OJvBJ33ccVZJ/ DtWn43FRrwGys0fISi1N9hqfYW4kXoRRFYsiSawjMlFuAMwJ7ejaQTlmGQr10HbB8ESo4wOEMFdJM KAS3y9BS+3oKtMAZSDt9XH/3UtZwWjt+tgFxs1F9+Pj2rjMn/0UUMKt7PosEdaXfRFsvQbq8A5Fyr 6rRs3xth/EA5i6NRsF/pRRHdz9lZ17rgDAV/GLksDMyIl51dDiyDzG2Z3VZFfNFZ/j/kusOqUA7RE Y0SU59+cYetPLvhTeN+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1maIyI-00DEmI-LO; Tue, 12 Oct 2021 14:41:38 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1maIyE-00DElK-TP for linux-arm-kernel@lists.infradead.org; Tue, 12 Oct 2021 14:41:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634049694; x=1665585694; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=uaKFVdc8S/VvWiZuXCUCkebK43ut9xuhbG5d0/Im4a4=; b=kbI6+nHosBQ9OCvaxLaD++uvkYC3ktxC8VDLSF4ZYIFGCWc/2ia8uQhw 0Zw1AV/8FXYzEarwe6msRVXljxZ95dK02KpT17O9qWoLCl7BwBN+jnM59 WGzjOVAK+TmuaX1IKDjOYXw8ReaJJ2nubEnplyiej0ku2vLfqFHvYPP0l mRas97c9O5rXc8yB0NUwbtlGtAd/F8qS4XEEKvUn1IxrCCQGW7fnC+L5w 7mWWOJI7D51syfWkegDLVuh8oFwfvZ8qpMUeF6Cgud++WmAkoYDcWgINg OrlURSJmjSXUe9Ue05Q9olrN41AvKxVCM93ASjKrgyDToQohPlLyRiNjR A==; IronPort-SDR: G5/0/w2zkA1J/kUitsL+TTmBuTT6zOQBYeRhnhdJ1xc+U88DRMABe9O5d/81kVSnERBHzCd2OA j8zVGqYj16GEvBA4cnAI/ethiQWXoh9KJ4Y8iQp1HPVPFQMYCceyuBO/KnJgXmx4hinrU9D7s3 h8wXxHdNWs7RfDwoRj9Ta6dJxGcVDy+0uynZhqJtGnFHj3FM5+BnVGDMVlF0B79k9T7s4XANfG IFxSKUYcQrmk58k87mAUHYVOyduXGMvW2TDUkJtAP9q4PDbplxLvgGuZdZUWBoRV062jl+zD8/ x5GK9Wb2BhJ62/SgcXMCGxhX X-IronPort-AV: E=Sophos;i="5.85,367,1624345200"; d="scan'208";a="132723629" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Oct 2021 07:41:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 12 Oct 2021 07:41:33 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 12 Oct 2021 07:41:33 -0700 Date: Tue, 12 Oct 2021 16:43:05 +0200 From: Horatiu Vultur To: Philipp Zabel CC: , , , , , , Subject: Re: [PATCH] pinctrl: microchip sgpio: use reset driver Message-ID: <20211012144305.cfvvtqlscnrhsvx2@soft-dev3-1.localhost> References: <20211012122435.2081930-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_074135_042682_ED1F04A8 X-CRM114-Status: GOOD ( 22.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Philipp, The 10/12/2021 15:40, Philipp Zabel wrote: > > On Tue, 2021-10-12 at 14:24 +0200, Horatiu Vultur wrote: > > On lan966x platform when the switch gets reseted then also the sgpio > > gets reseted. The fix for this is to extend also the sgpio driver to > > call the reset driver which will be reseted only once by the first > > driver that is probed. > > > > Signed-off-by: Horatiu Vultur > > --- > > drivers/pinctrl/pinctrl-microchip-sgpio.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c > > index 072bccdea2a5..e8a91d0824cb 100644 > > --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c > > +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c > > @@ -17,6 +17,7 @@ > > #include > > #include > > #include > > +#include > > > > #include "core.h" > > #include "pinconf.h" > > @@ -803,6 +804,7 @@ static int microchip_sgpio_probe(struct platform_device *pdev) > > int div_clock = 0, ret, port, i, nbanks; > > struct device *dev = &pdev->dev; > > struct fwnode_handle *fwnode; > > + struct reset_control *reset; > > struct sgpio_priv *priv; > > struct clk *clk; > > u32 val; > > @@ -813,6 +815,10 @@ static int microchip_sgpio_probe(struct platform_device *pdev) > > > > priv->dev = dev; > > > > + reset = devm_reset_control_get_shared(&pdev->dev, "switch"); > > This seems to be missing an update to the devicetree binding. Yes, I will fix this in the next version. > > Just to make sure we aren't introducing a circular dependency here, are > the PHY reset GPIOs that are toggled by the "switch" reset controller in > [1] provided by one of the sgpio controllers? > > [1] https://lore.kernel.org/all/20211012114238.2060101-3-horatiu.vultur@microchip.com/ Nope, the GPIOs are provided by a differnet gpio controller. > > regards > Philipp -- /Horatiu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel