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From: Mark Rutland <mark.rutland@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: alexandru.elisei@arm.com, andrii@kernel.org, ardb@kernel.org,
	ast@kernel.org, broonie@kernel.org, catalin.marinas@arm.com,
	daniel@iogearbox.net, dvyukov@google.com, james.morse@arm.com,
	jean-philippe@linaro.org, jpoimboe@redhat.com,
	mark.rutland@arm.com, maz@kernel.org, peterz@infradead.org,
	robin.murphy@arm.com, suzuki.poulose@arm.com, will@kernel.org
Subject: [PATCH 05/13] arm64: factor out GPR numbering helpers
Date: Wed, 13 Oct 2021 12:00:51 +0100	[thread overview]
Message-ID: <20211013110059.10324-6-mark.rutland@arm.com> (raw)
In-Reply-To: <20211013110059.10324-1-mark.rutland@arm.com>

In <asm/sysreg.h> we have macros to convert the names of general purpose
registers (GPRs) into integer constants, which we use to manually build
the encoding for `MRS` and `MSR` instructions where we can't rely on the
assembler to do so for us.

In subsequent patches we'll need to map the same GPR names to integer
constants so that we can use this to build metadata for exception
fixups.

So that the we can use the mappings elsewhere, factor out the
definitions into a new <asm/gpr-num.h> header, renaming the definitions
to align with this "GPR num" naming for clarity.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/gpr-num.h | 22 ++++++++++++++++++++++
 arch/arm64/include/asm/sysreg.h  | 25 ++++++++-----------------
 2 files changed, 30 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm64/include/asm/gpr-num.h

diff --git a/arch/arm64/include/asm/gpr-num.h b/arch/arm64/include/asm/gpr-num.h
new file mode 100644
index 000000000000..f936aa34dc63
--- /dev/null
+++ b/arch/arm64/include/asm/gpr-num.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_GPR_NUM_H
+#define __ASM_GPR_NUM_H
+
+#ifdef __ASSEMBLY__
+
+	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+	.equ	.L__gpr_num_x\num, \num
+	.endr
+	.equ	.L__gpr_num_xzr, 31
+
+#else /* __ASSEMBLY__ */
+
+#define __DEFINE_ASM_GPR_NUMS					\
+"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
+"	.equ	.L__gpr_num_x\\num, \\num\n"			\
+"	.endr\n"						\
+"	.equ	.L__gpr_num_xzr, 31\n"
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_GPR_NUM_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b268082d67ed..58f6e669dab4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -13,6 +13,8 @@
 #include <linux/stringify.h>
 #include <linux/kasan-tags.h>
 
+#include <asm/gpr-num.h>
+
 /*
  * ARMv8 ARM reserves the following encoding for system registers:
  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
@@ -1192,17 +1194,12 @@
 
 #ifdef __ASSEMBLY__
 
-	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
-	.equ	.L__reg_num_x\num, \num
-	.endr
-	.equ	.L__reg_num_xzr, 31
-
 	.macro	mrs_s, rt, sreg
-	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
+	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
 	.endm
 
 	.macro	msr_s, sreg, rt
-	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
+	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
 	.endm
 
 #else
@@ -1211,22 +1208,16 @@
 #include <linux/types.h>
 #include <asm/alternative.h>
 
-#define __DEFINE_MRS_MSR_S_REGNUM				\
-"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
-"	.equ	.L__reg_num_x\\num, \\num\n"			\
-"	.endr\n"						\
-"	.equ	.L__reg_num_xzr, 31\n"
-
 #define DEFINE_MRS_S						\
-	__DEFINE_MRS_MSR_S_REGNUM				\
+	__DEFINE_ASM_GPR_NUMS					\
 "	.macro	mrs_s, rt, sreg\n"				\
-	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))	\
+	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
 "	.endm\n"
 
 #define DEFINE_MSR_S						\
-	__DEFINE_MRS_MSR_S_REGNUM				\
+	__DEFINE_ASM_GPR_NUMS					\
 "	.macro	msr_s, sreg, rt\n"				\
-	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))	\
+	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
 "	.endm\n"
 
 #define UNDEFINE_MRS_S						\
-- 
2.11.0


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  parent reply	other threads:[~2021-10-13 12:21 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-13 11:00 [PATCH 00/13] arm64: extable: remove anonymous out-of-line fixups Mark Rutland
2021-10-13 11:00 ` [PATCH 01/13] arm64: lib: __arch_clear_user(): fold fixups into body Mark Rutland
2021-10-13 19:55   ` Robin Murphy
2021-10-14 11:09     ` Mark Rutland
2021-10-13 11:00 ` [PATCH 02/13] arm64: lib: __arch_copy_from_user(): " Mark Rutland
2021-10-13 11:00 ` [PATCH 03/13] arm64: lib: __arch_copy_to_user(): " Mark Rutland
2021-10-13 11:00 ` [PATCH 04/13] arm64: kvm: use kvm_exception_table_entry Mark Rutland
2021-10-13 11:00 ` Mark Rutland [this message]
2021-10-13 11:00 ` [PATCH 06/13] arm64: gpr-num: support W registers Mark Rutland
2021-10-13 11:00 ` [PATCH 07/13] arm64: extable: consolidate definitions Mark Rutland
2021-10-13 11:00 ` [PATCH 08/13] arm64: extable: make fixup_exception() return bool Mark Rutland
2021-10-13 11:00 ` [PATCH 09/13] arm64: extable: use `ex` for `exception_table_entry` Mark Rutland
2021-10-13 11:00 ` [PATCH 10/13] arm64: extable: add `type` and `data` fields Mark Rutland
2021-10-19 11:29   ` Will Deacon
2021-10-19 11:50     ` Mark Rutland
2021-10-19 12:05       ` Will Deacon
2021-10-19 12:12         ` Ard Biesheuvel
2021-10-19 13:01         ` Mark Rutland
2021-10-13 11:00 ` [PATCH 11/13] arm64: extable: add a dedicated uaccess handler Mark Rutland
2021-10-13 11:00 ` [PATCH 12/13] arm64: extable: add load_unaligned_zeropad() handler Mark Rutland
2021-10-13 11:00 ` [PATCH 13/13] arm64: vmlinux.lds.S: remove `.fixup` section Mark Rutland
2021-10-17 13:50 ` [PATCH 00/13] arm64: extable: remove anonymous out-of-line fixups Ard Biesheuvel

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