From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C756CC433F5 for ; Wed, 13 Oct 2021 17:32:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8989D610EA for ; Wed, 13 Oct 2021 17:32:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8989D610EA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1th5VzxyqDF+29HsjBwVTKz7IwtXAJPsHGaIS1t+S+M=; b=eiFvXy7FsFtNnp Dhg9+LUeew9afeS1fWWMZYe2b32LHlzQykP/KsrZM8wuO2scONXaKaQ8q6MWCW3i7DzLcbGLOcWEs gAlZOGJi66pnMxTrtcg6kjNZYFD11L0P41eq/X7oUYcc1gKAkRkK1NYnzAbN6SR9lRCRVgBLnJ/v2 4mFne1lP93MMOPAbC2TI43nEMpZtUXe6WinwcZ3nzYedr9/MdgJ5qTv298ZCiaEx7sqQ4hAdkmprk 1LYPe8TArQ107SECca45pdPCVmic40hvj0UdbF8SM2FP8Emj8mZrJj0wMrhQA6A2U0R+Gpz4LH2rI AdGI88ZOI8fuoIWqPRrw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mai5L-0009sL-17; Wed, 13 Oct 2021 17:30:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mai5G-0009rT-68 for linux-arm-kernel@lists.infradead.org; Wed, 13 Oct 2021 17:30:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE6B61063; Wed, 13 Oct 2021 10:30:26 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.73.189]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC1243F694; Wed, 13 Oct 2021 10:30:22 -0700 (PDT) Date: Wed, 13 Oct 2021 18:30:19 +0100 From: Mark Rutland To: Rob Herring Cc: Will Deacon , Peter Zijlstra , Ingo Molnar , Catalin Marinas , Arnaldo Carvalho de Melo , Jiri Olsa , Kan Liang , Ian Rogers , Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , Vince Weaver , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH v10 3/5] arm64: perf: Add userspace counter access disable switch Message-ID: <20211013173019.GC5400@C02TD0UTHF1T.local> References: <20210914204800.3945732-1-robh@kernel.org> <20210914204800.3945732-4-robh@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210914204800.3945732-4-robh@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211013_103030_332400_9C489FC2 X-CRM114-Status: GOOD ( 34.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 14, 2021 at 03:47:58PM -0500, Rob Herring wrote: > Like x86, some users may want to disable userspace PMU counter > altogether. Add a sysctl 'perf_user_access' file to control userspace > counter access. The default is '0' which is disabled. Writing '1' > enables access. > > Note that x86 also supports writing '2' to globally enable user access. For clarity it might be worth mentioning that on x86 this is controlled by the PMU's `rdpmc` sysfs attribute, i.e. Note that x86 supports globally enabling user access by writing '2' to /sys/bus/event_source/devices/cpu/rdpmc > As there's not existing userspace support to worry about, this shouldn't > be necessary for Arm. It could be added later if the need arises. > > Cc: Mark Rutland > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: Catalin Marinas > Cc: linux-perf-users@vger.kernel.org > Acked-by: Will Deacon > Signed-off-by: Rob Herring > --- > v10: > - Add documentation > - Use a custom handler (needed on the next patch) > v9: > - Use sysctl instead of sysfs attr > - Default to disabled > v8: > - New patch > --- > Documentation/admin-guide/sysctl/kernel.rst | 11 +++++++++ > arch/arm64/kernel/perf_event.c | 27 +++++++++++++++++++++ > 2 files changed, 38 insertions(+) > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index 426162009ce9..346a0dba5703 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -905,6 +905,17 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > The default value is 8. > > > +perf_user_access (arm64 only) > +================================= > + > +Controls user space access for reading perf event counters. When set to 1, > +user space can read performance monitor counter registers directly. > + > +The default value is 0 (access disabled). > + > +See Documentation/arm64/perf.rst for more information. Looking at the existing perf sysctls: # ls /proc/sys/kernel/perf* /proc/sys/kernel/perf_cpu_time_max_percent /proc/sys/kernel/perf_event_max_contexts_per_stack /proc/sys/kernel/perf_event_max_sample_rate /proc/sys/kernel/perf_event_max_stack /proc/sys/kernel/perf_event_mlock_kb /proc/sys/kernel/perf_event_paranoid I see that other than `perf_cpu_time_max_percent`, we've used `perf_event_` as the prefix, and I suspect we should do the same here, but I guess it may not matter either way. > + > + > pid_max > ======= > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index b4044469527e..a8f8dd741aeb 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -286,6 +286,8 @@ static const struct attribute_group armv8_pmuv3_events_attr_group = { > PMU_FORMAT_ATTR(event, "config:0-15"); > PMU_FORMAT_ATTR(long, "config1:0"); > > +static int sysctl_perf_user_access __read_mostly; > + > static inline bool armv8pmu_event_is_64bit(struct perf_event *event) > { > return event->attr.config1 & 0x1; > @@ -1104,6 +1106,29 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) > return probe.present ? 0 : -ENODEV; > } > > +int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write, > + void *buffer, size_t *lenp, loff_t *ppos) > +{ > + int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); > + if (ret || !write || sysctl_perf_user_access) > + return ret; > + > + return 0; > +} Maybe this is needed in the next patch, but the if statement is entirely redundant on this patch and looks really odd. Can we please either: 1) Use proc_dointvec_minmax() directly in this patch (which is what Will Acked in v9) and add the wrapper in the next patch when we need it. 2) make this: | int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write, | void *buffer, size_t *lenp, loff_t *ppos) | { | return proc_dointvec_minmax(table, write, buffer, lenp, ppos); | } ... and flesh it out in the next patch. With either of those two options (and regardless of whether the attribute is renamed): Reviewed-by: Mark Rutland Thanks, Mark. > + > + return 0; > +} > + > +static struct ctl_table armv8_pmu_sysctl_table[] = { > + { > + .procname = "perf_user_access", > + .data = &sysctl_perf_user_access, > + .maxlen = sizeof(unsigned int), > + .mode = 0644, > + .proc_handler = armv8pmu_proc_user_access_handler, > + .extra1 = SYSCTL_ZERO, > + .extra2 = SYSCTL_ONE, > + }, > + { } > +}; > + > static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, > int (*map_event)(struct perf_event *event), > const struct attribute_group *events, > @@ -1136,6 +1161,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, > cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ? > caps : &armv8_pmuv3_caps_attr_group; > > + register_sysctl("kernel", armv8_pmu_sysctl_table); > + > return 0; > } > > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel