From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Salil Akerkar <Salil.Akerkar@arm.com>,
Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH v3 40/42] kselftest/arm64: signal: Add SME signal handling tests
Date: Tue, 19 Oct 2021 18:22:45 +0100 [thread overview]
Message-ID: <20211019172247.3045838-41-broonie@kernel.org> (raw)
In-Reply-To: <20211019172247.3045838-1-broonie@kernel.org>
Add test cases for the SME signal handing ABI patterned off the SVE tests.
Due to the small size of the tests and the differences in ABI (especially
around needing to account for both streaming SVE and ZA) there is some code
duplication here.
We currently cover:
- Reporting of the vector length.
- Lack of support for changing vector length.
- Presence and size of register state for streaming SVE and ZA.
As with the SVE tests we do not yet have any validation of register
contents.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../testing/selftests/arm64/signal/.gitignore | 2 +
.../selftests/arm64/signal/test_signals.h | 2 +
.../arm64/signal/test_signals_utils.c | 3 +
.../testcases/fake_sigreturn_sme_change_vl.c | 92 +++++++++++++
.../arm64/signal/testcases/sme_trap_za.c | 36 +++++
.../selftests/arm64/signal/testcases/sme_vl.c | 70 ++++++++++
.../arm64/signal/testcases/ssve_regs.c | 129 ++++++++++++++++++
7 files changed, 334 insertions(+)
create mode 100644 tools/testing/selftests/arm64/signal/testcases/fake_sigreturn_sme_change_vl.c
create mode 100644 tools/testing/selftests/arm64/signal/testcases/sme_trap_za.c
create mode 100644 tools/testing/selftests/arm64/signal/testcases/sme_vl.c
create mode 100644 tools/testing/selftests/arm64/signal/testcases/ssve_regs.c
diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore
index c1742755abb9..4de8eb26d4de 100644
--- a/tools/testing/selftests/arm64/signal/.gitignore
+++ b/tools/testing/selftests/arm64/signal/.gitignore
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
mangle_*
fake_sigreturn_*
+sme_*
+ssve_*
sve_*
!*.[ch]
diff --git a/tools/testing/selftests/arm64/signal/test_signals.h b/tools/testing/selftests/arm64/signal/test_signals.h
index ebe8694dbef0..d0523a50ee78 100644
--- a/tools/testing/selftests/arm64/signal/test_signals.h
+++ b/tools/testing/selftests/arm64/signal/test_signals.h
@@ -34,11 +34,13 @@
enum {
FSSBS_BIT,
FSVE_BIT,
+ FSME_BIT,
FMAX_END
};
#define FEAT_SSBS (1UL << FSSBS_BIT)
#define FEAT_SVE (1UL << FSVE_BIT)
+#define FEAT_SME (1UL << FSME_BIT)
/*
* A descriptor used to describe and configure a test case.
diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.c b/tools/testing/selftests/arm64/signal/test_signals_utils.c
index 8bb12be87a51..cfb95010791a 100644
--- a/tools/testing/selftests/arm64/signal/test_signals_utils.c
+++ b/tools/testing/selftests/arm64/signal/test_signals_utils.c
@@ -27,6 +27,7 @@ static int sig_copyctx = SIGTRAP;
static char const *const feats_names[FMAX_END] = {
" SSBS ",
" SVE ",
+ " SME ",
};
#define MAX_FEATS_SZ 128
@@ -266,6 +267,8 @@ int test_init(struct tdescr *td)
td->feats_supported |= FEAT_SSBS;
if (getauxval(AT_HWCAP) & HWCAP_SVE)
td->feats_supported |= FEAT_SVE;
+ if (getauxval(AT_HWCAP2) & HWCAP2_SME)
+ td->feats_supported |= FEAT_SME;
if (feats_ok(td)) {
fprintf(stderr,
"Required Features: [%s] supported\n",
diff --git a/tools/testing/selftests/arm64/signal/testcases/fake_sigreturn_sme_change_vl.c b/tools/testing/selftests/arm64/signal/testcases/fake_sigreturn_sme_change_vl.c
new file mode 100644
index 000000000000..7ed762b7202f
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/fake_sigreturn_sme_change_vl.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 ARM Limited
+ *
+ * Attempt to change the streaming SVE vector length in a signal
+ * handler, this is not supported and is expected to segfault.
+ */
+
+#include <signal.h>
+#include <ucontext.h>
+#include <sys/prctl.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+struct fake_sigframe sf;
+static unsigned int vls[SVE_VQ_MAX];
+unsigned int nvls = 0;
+
+static bool sme_get_vls(struct tdescr *td)
+{
+ int vq, vl;
+
+ /*
+ * Enumerate up to SVE_VQ_MAX vector lengths
+ */
+ for (vq = SVE_VQ_MAX; vq > 0; --vq) {
+ vl = prctl(PR_SVE_SET_VL, vq * 16);
+ if (vl == -1)
+ return false;
+
+ vl &= PR_SME_VL_LEN_MASK;
+
+ /* Skip missing VLs */
+ vq = sve_vq_from_vl(vl);
+
+ vls[nvls++] = vl;
+ }
+
+ /* We need at least two VLs */
+ if (nvls < 2) {
+ fprintf(stderr, "Only %d VL supported\n", nvls);
+ return false;
+ }
+
+ return true;
+}
+
+static int fake_sigreturn_ssve_change_vl(struct tdescr *td,
+ siginfo_t *si, ucontext_t *uc)
+{
+ size_t resv_sz, offset;
+ struct _aarch64_ctx *head = GET_SF_RESV_HEAD(sf);
+ struct sve_context *sve;
+
+ /* Get a signal context with a SME ZA frame in it */
+ if (!get_current_context(td, &sf.uc))
+ return 1;
+
+ resv_sz = GET_SF_RESV_SIZE(sf);
+ head = get_header(head, SVE_MAGIC, resv_sz, &offset);
+ if (!head) {
+ fprintf(stderr, "No SVE context\n");
+ return 1;
+ }
+
+ if (head->size != sizeof(struct sve_context)) {
+ fprintf(stderr, "Register data present, aborting\n");
+ return 1;
+ }
+
+ sve = (struct sve_context *)head;
+
+ /* No changes are supported; init left us at minimum VL so go to max */
+ fprintf(stderr, "Attempting to change VL from %d to %d\n",
+ sve->vl, vls[0]);
+ sve->vl = vls[0];
+
+ fake_sigreturn(&sf, sizeof(sf), 0);
+
+ return 1;
+}
+
+struct tdescr tde = {
+ .name = "FAKE_SIGRETURN_SSVE_CHANGE",
+ .descr = "Attempt to change Streaming SVE VL",
+ .feats_required = FEAT_SME,
+ .sig_ok = SIGSEGV,
+ .timeout = 3,
+ .init = sme_get_vls,
+ .run = fake_sigreturn_ssve_change_vl,
+};
diff --git a/tools/testing/selftests/arm64/signal/testcases/sme_trap_za.c b/tools/testing/selftests/arm64/signal/testcases/sme_trap_za.c
new file mode 100644
index 000000000000..3a7747af4715
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/sme_trap_za.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 ARM Limited
+ *
+ * Verify that accessing ZA without enabling it generates a SIGILL.
+ */
+
+#include <signal.h>
+#include <ucontext.h>
+#include <sys/prctl.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+int sme_trap_za_trigger(struct tdescr *td)
+{
+ /* ZERO ZA */
+ asm volatile(".inst 0xc00800ff");
+
+ return 0;
+}
+
+int sme_trap_za_run(struct tdescr *td, siginfo_t *si, ucontext_t *uc)
+{
+ return 1;
+}
+
+struct tdescr tde = {
+ .name = "SME ZA trap",
+ .descr = "Check that we get a SIGILL if we access ZA without enabling",
+ .timeout = 3,
+ .sanity_disabled = true,
+ .trigger = sme_trap_za_trigger,
+ .run = sme_trap_za_run,
+ .sig_ok = SIGILL,
+};
diff --git a/tools/testing/selftests/arm64/signal/testcases/sme_vl.c b/tools/testing/selftests/arm64/signal/testcases/sme_vl.c
new file mode 100644
index 000000000000..c40e339a1bc3
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/sme_vl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 ARM Limited
+ *
+ * Check that the SME vector length reported in signal contexts is the
+ * expected one.
+ */
+
+#include <signal.h>
+#include <ucontext.h>
+#include <sys/prctl.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+struct fake_sigframe sf;
+unsigned int vl;
+
+static bool get_sme_vl(struct tdescr *td)
+{
+ int ret = prctl(PR_SME_GET_VL);
+ if (ret == -1)
+ return false;
+
+ vl = ret;
+
+ return true;
+}
+
+static int sme_vl(struct tdescr *td, siginfo_t *si, ucontext_t *uc)
+{
+ size_t resv_sz, offset;
+ struct _aarch64_ctx *head = GET_SF_RESV_HEAD(sf);
+ struct sve_context *sve;
+
+ /* Get a signal context which should have a SVE frame in it */
+ if (!get_current_context(td, &sf.uc))
+ return 1;
+
+ resv_sz = GET_SF_RESV_SIZE(sf);
+ head = get_header(head, SVE_MAGIC, resv_sz, &offset);
+ if (!head) {
+ fprintf(stderr, "No SVE context\n");
+ return 1;
+ }
+ sve = (struct sve_context *)head;
+
+ if (sve->vl != vl) {
+ fprintf(stderr, "SSVE sigframe VL %u, expected %u\n",
+ sve->vl, vl);
+ return 1;
+ } else {
+ fprintf(stderr, "got SSVE expected VL %u\n", vl);
+ }
+
+ /* Also check ZA VL */
+
+ td->pass = 1;
+
+ return 0;
+}
+
+struct tdescr tde = {
+ .name = "SME VL",
+ .descr = "Check that we get the right SME VL reported",
+ .feats_required = FEAT_SME,
+ .timeout = 3,
+ .init = get_sme_vl,
+ .run = sme_vl,
+};
diff --git a/tools/testing/selftests/arm64/signal/testcases/ssve_regs.c b/tools/testing/selftests/arm64/signal/testcases/ssve_regs.c
new file mode 100644
index 000000000000..44a08d43cd50
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/ssve_regs.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 ARM Limited
+ *
+ * Verify that the streaming SVE register context in signal frames is
+ * set up as expected.
+ */
+
+#include <signal.h>
+#include <ucontext.h>
+#include <sys/prctl.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+struct fake_sigframe sf;
+static unsigned int vls[SVE_VQ_MAX];
+unsigned int nvls = 0;
+
+static bool sme_get_vls(struct tdescr *td)
+{
+ int vq, vl;
+
+ /*
+ * Enumerate up to SVE_VQ_MAX vector lengths
+ */
+ for (vq = SVE_VQ_MAX; vq > 0; --vq) {
+ vl = prctl(PR_SVE_SET_VL, vq * 16);
+ if (vl == -1)
+ return false;
+
+ vl &= PR_SME_VL_LEN_MASK;
+
+ /* Skip missing VLs */
+ vq = sve_vq_from_vl(vl);
+
+ vls[nvls++] = vl;
+ }
+
+ /* We need at least one VL */
+ if (nvls < 1) {
+ fprintf(stderr, "Only %d VL supported\n", nvls);
+ return false;
+ }
+
+ return true;
+}
+
+static void setup_ssve_regs(void)
+{
+ /* SMSTART SM */
+ asm volatile(".inst 0x7f4303d5");
+
+ /* RDVL x16, #1 so we should have SVE regs; real data is TODO */
+ asm volatile(".inst 0x04bf5030" : : : "x16" );
+}
+
+static int do_one_sme_vl(struct tdescr *td, siginfo_t *si, ucontext_t *uc,
+ unsigned int vl)
+{
+ size_t resv_sz, offset;
+ struct _aarch64_ctx *head = GET_SF_RESV_HEAD(sf);
+ struct sve_context *ssve;
+
+ fprintf(stderr, "Testing VL %d\n", vl);
+
+ if (prctl(PR_SME_SET_VL, vl) == -1) {
+ fprintf(stderr, "Failed to set VL\n");
+ return 1;
+ }
+
+ /*
+ * Get a signal context which should have a SVE frame and registers
+ * in it.
+ */
+ setup_ssve_regs();
+ if (!get_current_context(td, &sf.uc))
+ return 1;
+
+ resv_sz = GET_SF_RESV_SIZE(sf);
+ head = get_header(head, SVE_MAGIC, resv_sz, &offset);
+ if (!head) {
+ fprintf(stderr, "No SVE context\n");
+ return 1;
+ }
+
+ ssve = (struct sve_context *)head;
+ if (ssve->vl != vl) {
+ fprintf(stderr, "Got VL %d, expected %d\n", ssve->vl, vl);
+ return 1;
+ }
+
+ /* The actual size validation is done in get_current_context() */
+ fprintf(stderr, "Got expected size %u and VL %d\n",
+ head->size, ssve->vl);
+
+ return 0;
+}
+
+static int sme_regs(struct tdescr *td, siginfo_t *si, ucontext_t *uc)
+{
+ int i;
+
+ for (i = 0; i < nvls; i++) {
+ /*
+ * TODO: the signal test helpers can't currently cope
+ * with signal frames bigger than struct sigcontext,
+ * skip VLs that will trigger that.
+ */
+ if (vls[i] > 64)
+ continue;
+
+ if (do_one_sme_vl(td, si, uc, vls[i]))
+ return 1;
+ }
+
+ td->pass = 1;
+
+ return 0;
+}
+
+struct tdescr tde = {
+ .name = "Streaming SVE registers",
+ .descr = "Check that we get the right Streaming SVE registers reported",
+ .feats_required = FEAT_SME,
+ .timeout = 3,
+ .init = sme_get_vls,
+ .run = sme_regs,
+};
--
2.30.2
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next prev parent reply other threads:[~2021-10-19 17:56 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 17:22 [PATCH v3 00/42] arm64/sme: Initial support for the Scalable Matrix Extension Mark Brown
2021-10-19 17:22 ` [PATCH v3 01/42] arm64/fp: Reindent fpsimd_save() Mark Brown
2021-10-19 17:22 ` [PATCH v3 02/42] arm64/sve: Remove sve_load_from_fpsimd_state() Mark Brown
2021-10-19 17:22 ` [PATCH v3 03/42] arm64/sve: Make sve_state_size() static Mark Brown
2021-10-19 17:22 ` [PATCH v3 04/42] arm64/sve: Make access to FFR optional Mark Brown
2021-10-19 17:22 ` [PATCH v3 05/42] arm64/sve: Rename find_supported_vector_length() Mark Brown
2021-10-19 17:22 ` [PATCH v3 06/42] arm64/sve: Use accessor functions for vector lengths in thread_struct Mark Brown
2021-10-19 17:22 ` [PATCH v3 07/42] arm64/sve: Put system wide vector length information into structs Mark Brown
2021-10-22 11:23 ` Catalin Marinas
2021-10-22 13:49 ` Mark Brown
2021-10-19 17:22 ` [PATCH v3 08/42] arm64/sve: Explicitly load vector length when restoring SVE state Mark Brown
2021-10-19 17:22 ` [PATCH v3 09/42] arm64/sve: Track vector lengths for tasks in an array Mark Brown
2021-10-19 17:22 ` [PATCH v3 10/42] arm64/sve: Make sysctl interface for SVE reusable by SME Mark Brown
2021-10-21 9:55 ` Will Deacon
2021-10-21 12:15 ` Mark Brown
2021-10-19 17:22 ` [PATCH v3 11/42] arm64/sve: Generalise vector length configuration prctl() for SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 12/42] kselftest/arm64: Parameterise ptrace vector length information Mark Brown
2021-10-19 17:22 ` [PATCH v3 13/42] kselftest/arm64: Allow signal tests to trigger from a function Mark Brown
2021-10-19 17:22 ` [PATCH v3 14/42] tools/nolibc: Implement gettid() Mark Brown
2021-10-19 17:22 ` [PATCH v3 15/42] arm64/sme: Provide ABI documentation for SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 16/42] arm64/sme: System register and exception syndrome definitions Mark Brown
2021-10-19 17:22 ` [PATCH v3 17/42] arm64/sme: Define macros for manually encoding SME instructions Mark Brown
2021-10-19 17:22 ` [PATCH v3 18/42] arm64/sme: Early CPU setup for SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 19/42] arm64/sme: Basic enumeration support Mark Brown
2021-10-19 17:22 ` [PATCH v3 20/42] arm64/sme: Identify supported SME vector lengths at boot Mark Brown
2021-10-19 17:22 ` [PATCH v3 21/42] arm64/sme: Implement sysctl to set the default vector length Mark Brown
2021-10-19 17:22 ` [PATCH v3 22/42] arm64/sme: Implement vector length configuration prctl()s Mark Brown
2021-10-19 17:22 ` [PATCH v3 23/42] arm64/sme: Implement support for TPIDR2 Mark Brown
2021-10-19 17:22 ` [PATCH v3 24/42] arm64/sme: Implement SVCR context switching Mark Brown
2021-10-19 17:22 ` [PATCH v3 25/42] arm64/sme: Implement streaming SVE " Mark Brown
2021-10-19 17:22 ` [PATCH v3 26/42] arm64/sme: Implement ZA " Mark Brown
2021-10-19 17:22 ` [PATCH v3 27/42] arm64/sme: Implement traps and syscall handling for SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 28/42] arm64/sme: Implement streaming SVE signal handling Mark Brown
2021-10-19 17:22 ` [PATCH v3 29/42] arm64/sme: Implement ZA " Mark Brown
2021-10-19 17:22 ` [PATCH v3 30/42] arm64/sme: Implement ptrace support for streaming mode SVE registers Mark Brown
2021-10-19 17:22 ` [PATCH v3 31/42] arm64/sme: Add ptrace support for ZA Mark Brown
2021-10-19 17:22 ` [PATCH v3 32/42] arm64/sme: Disable streaming mode and ZA when flushing CPU state Mark Brown
2021-10-19 17:22 ` [PATCH v3 33/42] arm64/sme: Save and restore streaming mode over EFI runtime calls Mark Brown
2021-10-19 17:22 ` [PATCH v3 34/42] arm64/sme: Provide Kconfig for SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 35/42] kselftest/arm64: sme: Add streaming SME support to vlset Mark Brown
2021-10-19 17:22 ` [PATCH v3 36/42] kselftest/arm64: Add tests for TPIDR2 Mark Brown
2021-10-19 17:22 ` [PATCH v3 37/42] kselftest/arm64: Extend vector configuration API tests to cover SME Mark Brown
2021-10-19 17:22 ` [PATCH v3 38/42] kselftest/arm64: sme: Provide streaming mode SVE stress test Mark Brown
2021-10-19 17:22 ` [PATCH v3 39/42] kselftest/arm64: Add stress test for SME ZA context switching Mark Brown
2021-10-19 17:22 ` Mark Brown [this message]
2021-10-19 17:22 ` [PATCH v3 41/42] kselftest/arm64: Add streaming SVE to SVE ptrace tests Mark Brown
2021-10-19 17:22 ` [PATCH v3 42/42] kselftest/arm64: Add coverage for the ZA ptrace interface Mark Brown
2021-10-21 10:05 ` [PATCH v3 00/42] arm64/sme: Initial support for the Scalable Matrix Extension Will Deacon
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