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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id d21sm3242747pfl.135.2021.10.20.08.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 08:42:09 -0700 (PDT) Date: Wed, 20 Oct 2021 09:42:07 -0600 From: Mathieu Poirier To: Suzuki K Poulose Cc: will@kernel.org, catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Message-ID: <20211020154207.GA3456574@p14s> References: <20211019163153.3692640-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211019163153.3692640-1-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_084214_055836_D15BBC06 X-CRM114-Status: GOOD ( 30.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > This series adds CPU erratum work arounds related to the self-hosted > tracing. The list of affected errata handled in this series are : > > * TRBE may overwrite trace in FILL mode > - Arm Neoverse-N2 #2139208 > - Cortex-A710 #211985 > > * A TSB instruction may not flush the trace completely when executed > in trace prohibited region. > > - Arm Neoverse-N2 #2067961 > - Cortex-A710 #2054223 > > * TRBE may write to out-of-range address > - Arm Neoverse-N2 #2253138 > - Cortex-A710 #2224489 > > The series applies on coresight/next. The series has been reordered > to make it easier to merge the patches via arm64 tree and the coresight > tree. > > Patches 1-4 are could be picked up via arm64 tree. The rest can go via > the coresight tree. The Kconfig items for the TRBE errata are initially > dropped in with dependency on COMPILE_TEST. These are dropped only after > the driver is equipped with the work around in later patches. > > > A tree is available here : > > git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v6 > > Changes since v5: > * https://lkml.kernel.org/r/20211014223125.2605031-1-suzuki.poulose@arm.com > - Fix typo in the Kconfig symbol usage in errata listing (Will) > - Fix typo in commit description for > "arm64: errata: Add detection for TRBE overwrite in FILL mode" > - Fix commit description checkpatch warnings on column length for: > "arm64: errata: Add detection for TRBE write to out-of-range" > - Collected Reviews/Acks from Mathieu/Anshuman/Will > > Changes since v4: > * https://lkml.kernel.org/r/20211012131743.2040596-1-suzuki.poulose@arm.com > > - Fix WARN on trbe driver probe on a hotplugged CPU, by making > sure that the arm_trbe_probe_cpu() is called from non-premptible > context. this_cpu_has_cap() doesn't like to be called from a > preemptible() context. > > - Fix Kconfig text issues pointed out by Randy > > Changes since v3: > > - Fix missing Kconfig selection for TSB flush failure erratum (Will) > Merged the Kconfig changes to the core patch for TSB. > - Use COMPILE_TEST dependency for the TRBE work arounds instead of > delaying the Kconfig entries. > > Changes since v2: > * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com > - Dropped patch adding a helper to reach cpudata from perf handle > - Split the TSB erratum work around patch to split the Kconfig/erratum > list update changes(pushed to the end of the series). > - Added wrappers to check the erratum : > trbe_has_erratum(cpudata, TRBE_ERRATUM_) -> trbe_may_<title> > - More ASCII art explanation on workaround. > > Changes since v1: > * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com > - Added a fix to the TRBE driver handling of sink_specific data > - Added more description and ASCII art for overwrite in FILL mode > work around > - Added another TRBE erratum to the list. > "TRBE may write to out-of-range address" > Patches from 12-17 > - Added comment to list the expectations around TSB erratum workaround. > > > > Suzuki K Poulose (15): > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > arm64: errata: Add detection for TRBE overwrite in FILL mode > arm64: errata: Add workaround for TSB flush failures > arm64: errata: Add detection for TRBE write to out-of-range > coresight: trbe: Add a helper to calculate the trace generated > coresight: trbe: Add a helper to pad a given buffer area > coresight: trbe: Decouple buffer base from the hardware base > coresight: trbe: Allow driver to choose a different alignment > coresight: trbe: Add infrastructure for Errata handling > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > coresight: trbe: Add a helper to determine the minimum buffer size > coresight: trbe: Make sure we have enough space > coresight: trbe: Work around write to out of range > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > arm64: errata: Enable TRBE workaround for write to out-of-range > address > > Documentation/arm64/silicon-errata.rst | 12 + > arch/arm64/Kconfig | 111 ++++++ > arch/arm64/include/asm/barrier.h | 16 +- > arch/arm64/include/asm/cputype.h | 4 + > arch/arm64/kernel/cpu_errata.c | 64 +++ > arch/arm64/tools/cpucaps | 3 + > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > 7 files changed, 567 insertions(+), 37 deletions(-) I have applied this set. Thanks, Mathieu > > -- > 2.25.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel