From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C14EC433EF for ; Mon, 25 Oct 2021 09:19:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6197B60EE9 for ; Mon, 25 Oct 2021 09:19:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6197B60EE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pk7GVNmFmFM6gr1aUSfbKAPSjyY5DJStGy8uRpHe9+I=; b=OtC0etOjb4go1r 3aLES0Iq2QUfdBkEVx4Pbsg5oSeSc12NwCXmydrfOxfbUoG8xSsDr/LgGqqla/gb5hqqcVViPT5f9 6XyiDEPJpwsJ9ZPzkuupeGH3IDJAaD3CWbcLQ8aOPIh7dVH43VJenV8FjYiTtTt8McyANaxilv2ev jGKk4B85H0QLOWKAoKm8rc8v6njadqkx5ZJ4sXT1tsuZQJ6IIiwWI1w9fWVBVKHI5ATaAo3YofL2L H6Uu59OWo6uSBosXz+u/5Qe0O/mNbM7dfrqOZrJUaV4gf1ayTRx8cs5BsD7Ny5Jk1LzAc3yl44bYl i41J+/1q40iCIcWTb9sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mew76-00FumS-3t; Mon, 25 Oct 2021 09:17:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mew72-00Ful7-59 for linux-arm-kernel@lists.infradead.org; Mon, 25 Oct 2021 09:17:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B47C92F; Mon, 25 Oct 2021 02:17:43 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.75.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 654D63F70D; Mon, 25 Oct 2021 02:17:40 -0700 (PDT) Date: Mon, 25 Oct 2021 10:17:31 +0100 From: Mark Rutland To: Brad Larson Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support Message-ID: <20211025091731.GA2001@C02TD0UTHF1T.local> References: <20211025015156.33133-1-brad@pensando.io> <20211025015156.33133-12-brad@pensando.io> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211025015156.33133-12-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211025_021748_284885_9FF6D5E6 X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > Add Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>; > + }; The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you have GICv3, where this is not valid, so this should go. Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which doesn't mak sense for the 16 CPUs you have. > + gic: interrupt-controller@800000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > + interrupts = ; > + > + gic_its: msi-controller@820000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x820000 0x0 0x10000>; > + socionext,synquacer-pre-its = > + <0xc00000 0x1000000>; > + }; > + }; Is there any shared lineage with Synquacer? The commit message didn't describe this quirk. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel