From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84208C433F5 for ; Thu, 11 Nov 2021 09:00:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C90961260 for ; Thu, 11 Nov 2021 09:00:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4C90961260 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MwL5Gc5Y26ZdFmLaBR+nXu0FEnjNf5EfWyCz/CZmvfQ=; b=XdaktzrSjuC7zH 8rJSRFi3wrO3ZPhwGkuFmB6Iz6J4cB7CsQy5EYQxLFe9Pa9v8Wy3Upi3M8jjDEqrEHSAkqE8R6/mo 09t7lfbdZ7VLnmzmVKct6Y26jBR2XZdzN0WJG469Kw3gusKsmoBZ6l2U53DW5Ks2nZIcoQcO5MXcK CbltZ3gZtzqdBoWuyYocHs5MVaake1GKC4ni/f4OnEqJuwMB4LJ30o7FAdVf07+2HSZlH0OiOrTeM L2f+XmyII4K5w/h2pbyMU/GidL3sACiCIYVAkHvjchHpL9u2KV/46HBeG3zCzJWLfEJ1nfGfJ/Xaa aS6J7W/5o/WSH2AO2x5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ml5vR-007Ye5-PB; Thu, 11 Nov 2021 08:59:17 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ml5vN-007Ycm-IE for linux-arm-kernel@lists.infradead.org; Thu, 11 Nov 2021 08:59:15 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8787B61208; Thu, 11 Nov 2021 08:59:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1636621153; bh=V/voYJdoZA1WY8AEKTOUrS/Vy3/qzbpOQsGhfSmMFw8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RDS3QmtEOrEJN86RtpjiUC0g3VTKJEznJ7GYHgWifBXd/43aiFvHghj+ZWzGVzR2k TIuFyfA+BOFkSbQcz6vfsnYkBtyDP/wEbl5ODtcAib3g/WqHphiMYGNqBFcy98j3jh upKkRms3N7wwml5TencLSL0R/0AiQeDPz9/hPNQPp3L2eRmnl2CinLtG2lUzV39WuY TkkcKZYza+f7g+sDZyEcbgqIGc+tUMLZ2KZaq5j4FKlT59z+paZLRdOgI1xl6tqN4h +95phXRgsnqqOegHYylKgiublk3jCaXmTmm9b+bo2G4V75SiDf4uKyqPtd1vWXkhVc E1eGCsxbbz4yA== Date: Thu, 11 Nov 2021 08:59:08 +0000 From: Will Deacon To: Yu Zhao Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, page-reclaim@google.com, holger@applied-asynchrony.com, iam@valdikss.org.ru, Konstantin Kharlamov , catalin.marinas@arm.com Subject: Re: [PATCH v5 01/10] mm: x86, arm64: add arch_has_hw_pte_young() Message-ID: <20211111085907.GA5407@willie-the-truck> References: <20211111041510.402534-1-yuzhao@google.com> <20211111041510.402534-2-yuzhao@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211111041510.402534-2-yuzhao@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211111_005913_642630_FF689B32 X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 10, 2021 at 09:15:01PM -0700, Yu Zhao wrote: > Some architectures automatically set the accessed bit in PTEs, e.g., > x86 and arm64 v8.2. On architectures that do not have this capability, > clearing the accessed bit in a PTE triggers a page fault following the > TLB miss of this PTE. > > Being aware of this capability can help make better decisions, i.e., > whether to limit the size of each batch of PTEs and the burst of > batches when clearing the accessed bit. > > Signed-off-by: Yu Zhao > Tested-by: Konstantin Kharlamov > --- > arch/arm64/include/asm/cpufeature.h | 5 +++++ > arch/arm64/include/asm/pgtable.h | 13 ++++++++----- > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > arch/x86/include/asm/pgtable.h | 6 +++--- > include/linux/pgtable.h | 13 +++++++++++++ > mm/memory.c | 14 +------------- > 7 files changed, 41 insertions(+), 21 deletions(-) *Please* cc the maintainers on arch patches. I asked you that last time, too: https://lore.kernel.org/r/20210819091923.GA15467@willie-the-truck > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6ec7036ef7e1..940615d33845 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2157,6 +2157,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_hw_dbm, > .cpu_enable = cpu_enable_hw_dbm, > }, > + { > + .desc = "Hardware update of the Access flag", > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .capability = ARM64_HW_AF, > + .sys_reg = SYS_ID_AA64MMFR1_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR1_HADBS_SHIFT, > + .min_field_value = 1, > + .matches = has_cpuid_feature, > + }, As before, please don't make this a system feature as it will prohibit onlining of late CPUs with mismatched access flag support and I really don't see that being necessary. You should just be able to use arch_faults_on_old_pte() as-is. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel