From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22372C433EF for ; Wed, 17 Nov 2021 11:40:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7E4961BFE for ; Wed, 17 Nov 2021 11:40:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C7E4961BFE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xu+TLBnXLxZ9wKPjZTkN642XjSO4abCXzoF9jolA9dQ=; b=wvwdb4ShZDQ65S 2fiIqv2QFmZZXfXpNqChuczkrJxv6Qi0QI7zmMIBCZqKmrP08CzQx1mee6KxRkyq/nwuEskaNAtSf BRVNAO3UXlzX2GmJ7geAcPI1PC90hKcPPWFNmgEenbNHY78kx9ii8wlGvbxR17zntp63ZR2ws6FTr WvcB+t6EsjYrbVqlqWKspIy00fsOVUrcV+3CgM7Z0CyY0s/xfBBy26OC0BQKFMkGW7KUz+1o7MQUK OYM9swStYydRk1yYO9UDpp/28DwqJoZM0703GD6kvp8x8R0I56S0FNaEI9OHPOnYk+Noh+xNGwv4t x8H1h/4egqDH/jT7HbVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnJHU-004dHF-U6; Wed, 17 Nov 2021 11:39:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnJHP-004dDp-1x for linux-arm-kernel@lists.infradead.org; Wed, 17 Nov 2021 11:39:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24A1A1FB; Wed, 17 Nov 2021 03:39:03 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.46.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 43E953F70D; Wed, 17 Nov 2021 03:39:01 -0800 (PST) Date: Wed, 17 Nov 2021 11:38:54 +0000 From: Mark Rutland To: Pingfan Liu Cc: linux-arm-kernel@lists.infradead.org, "Paul E . McKenney" , Catalin Marinas , Will Deacon , Marc Zyngier , Thomas Gleixner , Joey Gouly , Sami Tolvanen , Julien Thierry , Yuichi Ito , rcu@vger.kernel.org Subject: Re: [PATCHv3 1/4] arm64: entry: judge nmi ealier to avoid deadlock in RCU Message-ID: <20211117113854.GA41542@C02TD0UTHF1T.local> References: <20211116082450.10357-1-kernelfans@gmail.com> <20211116082450.10357-2-kernelfans@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211116082450.10357-2-kernelfans@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211117_033907_255021_59878449 X-CRM114-Status: GOOD ( 34.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 16, 2021 at 04:24:47PM +0800, Pingfan Liu wrote: > Linux kernel places strict semantics between NMI and maskable interrupt. > So does the RCU component, else deadlock may happen. But the current > arm64 entry code can partially breach this rule through calling > rcu_nmi_enter(). > > *** how a deadlock can happen if NMI mistaken as IRQ *** > > rcu_nmi_enter() > { > > if (rcu_dynticks_curr_cpu_in_eqs()) { > > if (!in_nmi()) > rcu_dynticks_task_exit(); > ... > if (!in_nmi()) { > instrumentation_begin(); > rcu_cleanup_after_idle(); > instrumentation_end(); > } > ... > } else if (!in_nmi()) { > instrumentation_begin(); > rcu_irq_enter_check_tick(); > } > > } > > If a NMI is mistaken as a maskable interrupt, rcu_irq_enter_check_tick() > can hit a deadlock, which is demonstrated by the following scenario: > > note_gp_changes() runs in a task context > { > local_irq_save(flags); // this protects against irq, but not NMI Note: speecifically, this masks IRQs via ICC_PMR_EL1. > rnp = rdp->mynode; > ... > raw_spin_trylock_rcu_node(rnp) > -------> broken in by (p)NMI, without taking __nmi_enter() AFAICT the broken case described here *cannot* happen. If we take a pNMI here, we'll go: el1h_64_irq() -> el1h64_irq_handler() -> el1_interrupt() ... where el1_interrupt is: | static void noinstr el1_interrupt(struct pt_regs *regs, | void (*handler)(struct pt_regs *)) | { | write_sysreg(DAIF_PROCCTX_NOIRQ, daif); | | if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs)) | __el1_pnmi(regs, handler); | else | __el1_irq(regs, handler); | } ... and interrupts_enabled() is: | #define interrupts_enabled(regs) \ | (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) ... and irqs_priority_unmasked is: | #define irqs_priority_unmasked(regs) \ | (system_uses_irq_prio_masking() ? \ | (regs)->pmr_save == GIC_PRIO_IRQON : \ | true) ... irqs_priority_unmasked(regs) *must* return false for this case, since the local_irq_save() above must have set the PMR to GIC_PRIO_IRQOFF in the interrupted context. Thus, we *must* call __el1_pnmi() in this case, where __el1_pnmi() is: | static __always_inline void __el1_pnmi(struct pt_regs *regs, | void (*handler)(struct pt_regs *)) | { | arm64_enter_nmi(regs); | do_interrupt_handler(regs, handler); | arm64_exit_nmi(regs); | } Note that arm64_{enter,exit}_nmi() handle the __nmi_{enter,exit}() calls around do_interupt_handler(). > rcu_nmi_enter() > ->__rcu_irq_enter_check_tick() > ->raw_spin_lock_rcu_node(rdp->mynode); > deadlock happens!!! > > } As above, I don't think this can go wrong as you describe, and don't believe that this can deadlock. > *** On arm64, how pNMI mistaken as IRQ *** > > On arm64, pNMI is an analogue to NMI. In essence, it is a higher > priority interrupt but not disabled by local_irq_disable(). > > In current implementation > 1) If a pNMI from a context where IRQs were masked, it can be recognized > as nmi, and calls __nmi_enter() immediately. This is no problem. Agreed, this case works correctly. > 2) But it causes trouble if a pNMI from a context where IRQs were > unmasked, and temporarily regarded as maskable interrupt. It is not > treated as NMI, i.e. calling nmi_enter() until reading from GIC. > > __el1_irq() > { > irq_enter_rcu() ----> hit the deadlock bug What is "the deadlock bug"? The example you had above was for a context where IRQs were *masked*, which is a different case. Consider that if this can happen for a context where IRQs are unmasked it means that we would also deadlock *when taking a regular IRQ*. I do not beleive that this can deadlock as described. I don't see this as any different from a sequence such as: < run in a context with IRQs unmasked> < take a regular IRQ > < take a pNMI within the IRQ handling flow > ... e.g. taking a pNMI when handling a spurious regular IRQ. > gic_handle_nmi() > nmi_enter() > nmi_exit() > irq_exit_rcu() > } > > *** Remedy *** > > If the irqchip level exposes an interface for detecting pNMI to arch level > code, it can meet the requirement at this early stage. That is the > interface (*interrupt_is_nmi)() in this patch. As above, I do not believe that this is necessary for the current pseudo-NMI scheme. Are you seeing a deadlock in practice, or is this something you've found by inspection? Thanks, Mark. > Signed-off-by: Pingfan Liu > Cc: Mark Rutland > Cc: Paul E. McKenney > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Thomas Gleixner > Cc: Joey Gouly > Cc: Sami Tolvanen > Cc: Julien Thierry > Cc: Yuichi Ito > Cc: rcu@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/include/asm/irq.h | 1 + > arch/arm64/kernel/entry-common.c | 10 +++++++++- > arch/arm64/kernel/irq.c | 18 ++++++++++++++++++ > 3 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h > index fac08e18bcd5..f3eb13bfa65e 100644 > --- a/arch/arm64/include/asm/irq.h > +++ b/arch/arm64/include/asm/irq.h > @@ -11,6 +11,7 @@ struct pt_regs; > int set_handle_irq(void (*handle_irq)(struct pt_regs *)); > #define set_handle_irq set_handle_irq > int set_handle_fiq(void (*handle_fiq)(struct pt_regs *)); > +int set_nmi_discriminator(bool (*discriminator)(void)); > > static inline int nr_legacy_irqs(void) > { > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > index f7408edf8571..5a1a5dd66d04 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -260,6 +260,14 @@ static void do_interrupt_handler(struct pt_regs *regs, > > extern void (*handle_arch_irq)(struct pt_regs *); > extern void (*handle_arch_fiq)(struct pt_regs *); > +extern bool (*interrupt_is_nmi)(void); > + > +static inline bool is_in_pnmi(struct pt_regs *regs) > +{ > + if (!interrupts_enabled(regs) || (*interrupt_is_nmi)()) > + return true; > + return false; > +} > > static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector, > unsigned int esr) > @@ -454,7 +462,7 @@ static void noinstr el1_interrupt(struct pt_regs *regs, > { > write_sysreg(DAIF_PROCCTX_NOIRQ, daif); > > - if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs)) > + if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && is_in_pnmi(regs)) > __el1_pnmi(regs, handler); > else > __el1_irq(regs, handler); > diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c > index bda49430c9ea..fabed09ed966 100644 > --- a/arch/arm64/kernel/irq.c > +++ b/arch/arm64/kernel/irq.c > @@ -81,8 +81,14 @@ static void default_handle_fiq(struct pt_regs *regs) > panic("FIQ taken without a root FIQ handler\n"); > } > > +static bool default_nmi_discriminator(void) > +{ > + return false; > +} > + > void (*handle_arch_irq)(struct pt_regs *) __ro_after_init = default_handle_irq; > void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init = default_handle_fiq; > +bool (*interrupt_is_nmi)(void) __ro_after_init = default_nmi_discriminator; > > int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) > { > @@ -104,6 +110,18 @@ int __init set_handle_fiq(void (*handle_fiq)(struct pt_regs *)) > return 0; > } > > +#if IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) > + > +int __init set_nmi_discriminator(bool (*discriminator)(void)) > +{ > + if (interrupt_is_nmi != default_nmi_discriminator) > + return -EBUSY; > + > + interrupt_is_nmi = discriminator; > + return 0; > +} > +#endif > + > void __init init_IRQ(void) > { > init_irq_stacks(); > -- > 2.31.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel