From: "Pali Rohár" <pali@kernel.org>
To: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Marek Behún" <kabel@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
Date: Wed, 24 Nov 2021 16:59:40 +0100 [thread overview]
Message-ID: <20211124155944.1290-3-pali@kernel.org> (raw)
In-Reply-To: <20211124155944.1290-1-pali@kernel.org>
Some bits in PCI config space are reserved when device is PCIe. Properly
define behavior of PCI registers for PCIe emulated bridge and ensure that
it would not be possible change these reserved bits.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
Cc: stable@vger.kernel.org
---
drivers/pci/pci-bridge-emul.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 5de8b8dde209..0cbb4e3ca827 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -295,6 +295,27 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
kfree(bridge->pci_regs_behavior);
return -ENOMEM;
}
+ /* These bits are applicable only for PCI and reserved on PCIe */
+ bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
+ ~GENMASK(15, 8);
+ bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
+ ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
+ PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
+ PCI_COMMAND_FAST_BACK) |
+ (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+ PCI_STATUS_DEVSEL_MASK) << 16);
+ bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
+ ~GENMASK(31, 24);
+ bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
+ ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+ PCI_STATUS_DEVSEL_MASK) << 16);
+ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
+ ~((PCI_BRIDGE_CTL_MASTER_ABORT |
+ BIT(8) | BIT(9) | BIT(11)) << 16);
+ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
+ ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
+ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
+ ~(BIT(10) << 16);
}
if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
--
2.20.1
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next prev parent reply other threads:[~2021-11-24 16:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-24 15:59 [PATCH 0/6] PCI: pci-bridge-emul: Various fixes Pali Rohár
2021-11-24 15:59 ` [PATCH 1/6] PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only Pali Rohár
2021-11-24 15:59 ` Pali Rohár [this message]
2021-11-24 15:59 ` [PATCH 3/6] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Pali Rohár
2021-11-24 15:59 ` [PATCH 4/6] PCI: pci-bridge-emul: Fix definitions of reserved bits Pali Rohár
2021-11-24 15:59 ` [PATCH 5/6] PCI: pci-bridge-emul: Correctly set PCIe capabilities Pali Rohár
2021-11-24 15:59 ` [PATCH 6/6] PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device Pali Rohár
2021-11-30 13:26 ` [PATCH 0/6] PCI: pci-bridge-emul: Various fixes Marek Behún
2021-12-02 20:20 ` Pali Rohár
2021-12-06 12:19 ` Lorenzo Pieralisi
2021-12-06 12:24 ` Pali Rohár
2021-12-06 14:26 ` Lorenzo Pieralisi
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