Re: [PATCH v4 10/12] ARM: dts: Add PCIe support for Airoha EN7523

Jianjun Wang
2021-11-25T12:17:40Z

Hi Felix,

On Thu, 2021-11-25 at 12:07 +0100, Felix Fietkau wrote:
> This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is
> nearly
> identical to the one in MT7622
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> arch/arm/boot/dts/en7523-evb.dts | 12 +++++++
> arch/arm/boot/dts/en7523.dtsi | 60
> ++++++++++++++++++++++++++++++++
> 2 files changed, 72 insertions(+)
>
> diff --git a/arch/arm/boot/dts/en7523-evb.dts
> b/arch/arm/boot/dts/en7523-evb.dts
> index e8e5c034cee7..af1a8dd40a41 100644
> --- a/arch/arm/boot/dts/en7523-evb.dts
> +++ b/arch/arm/boot/dts/en7523-evb.dts
> @@ -25,3 +25,15 @@ memory@80000000 {
> reg = <0x80000000 0x20000000>;
> };
> };
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/en7523.dtsi
> b/arch/arm/boot/dts/en7523.dtsi
> index eabf3fdb3d52..d9bdb51614b5 100644
> --- a/arch/arm/boot/dts/en7523.dtsi
> +++ b/arch/arm/boot/dts/en7523.dtsi
> @@ -119,4 +119,64 @@ uart1: serial@1fbf0000 {
> clock-frequency = <1843200>;
> status = "okay";
> };
> +
> + pcie: pcie@1a140000 {
> + compatible = "airoha,en7523-pcie", "mediatek,mt7622-
> pcie";
> + device_type = "pci";
> + reg = <0x1fa91000 0x1000>,
> + <0x1fa92000 0x1000>;
> + reg-names = "port0", "port1";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scu EN7523_CLK_PCIE>,
> + <&scu EN7523_CLK_PCIE>;
> + clock-names = "sys_ck0", "sys_ck1";
> + bus-range = <0x00 0xff>;
> + ranges = <0x82000000 0 0x20000000 0x20000000 0
> 0x10000000>;
> + status = "disabled";
> +
> + pcie0: pcie@0,0 {
> + device_type = "pci";
> + reg = <0x0000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> + <0 0 0 2 &pcie_intc0 1>,
> + <0 0 0 3 &pcie_intc0 2>,
> + <0 0 0 4 &pcie_intc0 3>;
> + pcie_intc0: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + pcie1: pcie@1,0 {
> + device_type = "pci";
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> + pcie_intc1: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };

There are some known issues with this device node style, please split
the PCIe node into two independent nodes to comply with the hardware
design.

Here is the fix patch we sent before:

https://lore.kernel.org/linux-pci/20210823032800.1660-6-chuanjia.liu@mediatek.com/

Thanks.

> };