From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Nicolas Pitre <nico@fluxnic.net>, Arnd Bergmann <arnd@arndb.de>,
Kees Cook <keescook@chromium.org>,
Keith Packard <keithpac@amazon.com>,
Linus Walleij <linus.walleij@linaro.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tony Lindgren <tony@atomide.com>
Subject: [RFC PATCH 4/6] ARM: smp: defer TPIDRURO update for SMP v6 configurations too
Date: Fri, 26 Nov 2021 11:10:04 +0100 [thread overview]
Message-ID: <20211126101006.3410322-5-ardb@kernel.org> (raw)
In-Reply-To: <20211126101006.3410322-1-ardb@kernel.org>
Defer TPIDURO updates for user space until exit for CPU_V6+SMP
configurations as well so that we can decide at runtime whether to use
it to carry the current pointer, provided that we are running on a CPU
that actually implements this register. This is needed for
THREAD_INFO_IN_TASK support for UP systems, which requires that all SMP
capable systems use the TPIDRURO based access to 'current' as the only
remaining alternative will be a global variable which only work on UP.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm/include/asm/tls.h | 4 +++-
| 8 +++++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index c3296499176c..9c0965c14a21 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -24,7 +24,9 @@
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
+#ifndef CONFIG_SMP
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
+#endif
mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
.endm
@@ -43,7 +45,7 @@
#elif defined(CONFIG_CPU_V6)
#define tls_emu 0
#define has_tls_reg (elf_hwcap & HWCAP_TLS)
-#define defer_tls_reg_update 0
+#define defer_tls_reg_update IS_ENABLED(CONFIG_SMP)
#define switch_tls switch_tls_v6
#elif defined(CONFIG_CPU_32v6K)
#define tls_emu 0
--git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 81df2a3561ca..aea716c8b97c 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -292,12 +292,18 @@
.macro restore_user_regs, fast = 0, offset = 0
-#if defined(CONFIG_CPU_32v6K) && !defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_32v6K) || \
+ (defined(CONFIG_CPU_V6) && defined(CONFIG_SMP))
@ The TLS register update is deferred until return to user space so we
@ can use it for other things while running in the kernel
+#ifdef CONFIG_CPU_V6
+ALT_SMP(nop)
+ALT_UP_B(.L0_\@)
+#endif
get_thread_info r1
ldr r1, [r1, #TI_TP_VALUE]
mcr p15, 0, r1, c13, c0, 3 @ set TLS register
+.L0_\@:
#endif
uaccess_enable r1, isb=0
--
2.30.2
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next prev parent reply other threads:[~2021-11-26 10:13 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 10:10 [RFC PATCH 0/6] ARM: enable IRQ stacks and vmap'ed stacks for UP Ard Biesheuvel
2021-11-26 10:10 ` [RFC PATCH 1/6] ARM: entry: preserve thread_info pointer in switch_to Ard Biesheuvel
2021-11-26 10:10 ` [RFC PATCH 2/6] ARM: module: implement support for PC-relative group relocations Ard Biesheuvel
2021-11-26 10:10 ` [RFC PATCH 3/6] ARM: percpu: add SMP_ON_UP support Ard Biesheuvel
2021-11-26 10:10 ` Ard Biesheuvel [this message]
2021-11-26 10:10 ` [RFC PATCH 5/6] ARM: use TLS register for 'current' on !SMP as well Ard Biesheuvel
2021-11-26 10:10 ` [RFC PATCH 6/6] ARM: implement THREAD_INFO_IN_TASK for uniprocessor systems Ard Biesheuvel
2021-11-26 22:32 ` Arnd Bergmann
2021-11-30 8:00 ` Ard Biesheuvel
2021-11-27 0:20 ` [RFC PATCH 0/6] ARM: enable IRQ stacks and vmap'ed stacks for UP Linus Walleij
2021-11-29 16:32 ` Nicolas Pitre
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