From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7DB5C433F5 for ; Tue, 30 Nov 2021 13:01:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Xc7XR2hyqzo/tu0x9XvRFC9CNlRgwJhv21HX58a0rIY=; b=0Y4QtKksJgzwn/ hbpPlzPfqMxexmFD/iIGsgpXFea0vpfdVn8utt8Fn2yUV9hCUeab/BRYjjQO8QzT3vN/9W5OWnfll JFh6jLhhkAAGCEe07N1Dy5Sbr+vHri2J2Q+ofSE/PPsTYXf4AUHR1Mu9cpgtoiGj6mqdIe7bwcEjG 7ppXQ1MZwz0pe5ofZlXNIeC0kmE5MsgYVqbRCkEQZTr1v/9zGLtAZkZYajRvzxW3oD420qM+iuuSW HbviYYYw7Yp9ahXaCuPyYPNjxDIoE91KrCgKrEotjRaEtQvI7alxFcMWT6yAYMGjbseCucMxio6kK kLZO9mIrSILrR9f+IaCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ms2jj-005CXe-JJ; Tue, 30 Nov 2021 12:59:56 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ms2jA-005CLs-Em for linux-arm-kernel@lists.infradead.org; Tue, 30 Nov 2021 12:59:22 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1EE53B8166D; Tue, 30 Nov 2021 12:59:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA45DC53FCF; Tue, 30 Nov 2021 12:59:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638277157; bh=T6rpDtmTTc9Apkt0RBHSNonIYvBzepHOlHSLEAM7Eg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LCoe3go6rwkMjNWXKjMC0eXbcyaYdrtOEL5EvS+J7MAskvHGZ6qMkIXdEfbM2140p 7kwD60HpO4Ap5V7PRrYJG1/KklxPTqgYCDHxK+57v9p06b8ZLdvOU7qN41XC9LZvP0 IDN7+a1QDKW3l9VZO5J5GOAARwJvul3GQnd4Gf7X8I9RxrMA96rB1I9+P+CONKAxoY 2eRp54FMb5xDhR2xFG4KL5d5CG5aSvROgF6aJsfh/XkOhEROsnnoMYfkxsiJ8y+I75 CSf47lX8FMdcRP5UwHdc1gCH1zz5sZxVFmq0FgmOBFThpT/3iNM5I2Vmg98m4WY24B XVYRuj6tywEog== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk Cc: Ard Biesheuvel , Nicolas Pitre , Arnd Bergmann , Kees Cook , Keith Packard , Linus Walleij , Nick Desaulniers , Tony Lindgren Subject: [PATCH v2 03/12] ARM: iop32x: offset IRQ numbers by 1 Date: Tue, 30 Nov 2021 13:58:52 +0100 Message-Id: <20211130125901.3054-4-ardb@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211130125901.3054-1-ardb@kernel.org> References: <20211130125901.3054-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4121; i=ardb@kernel.org; h=from:subject; bh=98KWL5Q18cUTlqiEVJa1Tliza5bRwPIVxrSCuyzWoOk=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBhpiAKvI6/1egtonZCKNtFSWXs5bb1WWKgeEhvpGvS +/G8YQmJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCYaYgCgAKCRDDTyI5ktmPJM+pC/ 9GAm3CEScq2k4Vgs7NC7xGT6A1sYQWker1pQADXYJA/Yg7P63fH/HoVSaHpRc/3rFdII/1n8XJYwqf 1kqVKWRDPJi18GOWauNIXHbUxbseQvcrFTI1GdgnLD1ClujDELE//mP/HG9zEDk1HQ235dMksmPBQn 6Z7vAN8q/Iju7ya0okOSTgVHOS+0W/Prf2bv9g5ynz/2LAfYsfvAV0Mymm+i/o8IbMzS4rvUIEgULS RDRNIRv4A6zGztG7wvXj/XDZWrWZ5iT0hggbMVCEVHGgh+o2rda41vp2iLZ+UP+BTrE2KnMQJwerAu TDE/cFVzUPAqRllcvnEcB7pV1JBFBxJQk+phEMKlxM3F4g3VQAKpe8tQUTE4q9sQ9WoeDND0hgvnod W5nXiH3TodtBEK5UVpgqea4jZisJmd0p7InflKd1/kicjw4258WTtT8ZtUsNs7q8tOT2umoElw1y+R V3Z2DIXFQ2LAXjB6jF/t1y5+Oz+vrsTaF6trHTxYgOZq0= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211130_045920_815579_2C9D0FA0 X-CRM114-Status: GOOD ( 15.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arnd Bergmann iop32x is one of the last platforms to use IRQ 0, and this has apparently stopped working in a 2014 cleanup without anyone noticing. This interrupt is used for the DMA engine, so most likely this has not actually worked in the past 7 years, but it's also not essential for using this board. I'm splitting out this change from my GENERIC_IRQ_MULTI_HANDLER conversion so it can be backported if anyone cares. Fixes: a71b092a9c68 ("ARM: Convert handle_IRQ to use __handle_domain_irq") Signed-off-by: Arnd Bergmann Signed-off-by: Ard Biesheuvel --- arch/arm/mach-iop32x/include/mach/entry-macro.S | 2 +- arch/arm/mach-iop32x/include/mach/irqs.h | 2 +- arch/arm/mach-iop32x/irqs.h | 60 +++++++++++--------- 3 files changed, 34 insertions(+), 30 deletions(-) diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S index 8e6766d4621e..341e5d9a6616 100644 --- a/arch/arm/mach-iop32x/include/mach/entry-macro.S +++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S @@ -20,7 +20,7 @@ mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC cmp \irqstat, #0 clzne \irqnr, \irqstat - rsbne \irqnr, \irqnr, #31 + rsbne \irqnr, \irqnr, #32 .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h index c4e78df428e8..e09ae5f48aec 100644 --- a/arch/arm/mach-iop32x/include/mach/irqs.h +++ b/arch/arm/mach-iop32x/include/mach/irqs.h @@ -9,6 +9,6 @@ #ifndef __IRQS_H #define __IRQS_H -#define NR_IRQS 32 +#define NR_IRQS 33 #endif diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h index 69858e4e905d..e1dfc8b4e7d7 100644 --- a/arch/arm/mach-iop32x/irqs.h +++ b/arch/arm/mach-iop32x/irqs.h @@ -7,36 +7,40 @@ #ifndef __IOP32X_IRQS_H #define __IOP32X_IRQS_H +/* Interrupts in Linux start at 1, hardware starts at 0 */ + +#define IOP_IRQ(x) ((x) + 1) + /* * IOP80321 chipset interrupts */ -#define IRQ_IOP32X_DMA0_EOT 0 -#define IRQ_IOP32X_DMA0_EOC 1 -#define IRQ_IOP32X_DMA1_EOT 2 -#define IRQ_IOP32X_DMA1_EOC 3 -#define IRQ_IOP32X_AA_EOT 6 -#define IRQ_IOP32X_AA_EOC 7 -#define IRQ_IOP32X_CORE_PMON 8 -#define IRQ_IOP32X_TIMER0 9 -#define IRQ_IOP32X_TIMER1 10 -#define IRQ_IOP32X_I2C_0 11 -#define IRQ_IOP32X_I2C_1 12 -#define IRQ_IOP32X_MESSAGING 13 -#define IRQ_IOP32X_ATU_BIST 14 -#define IRQ_IOP32X_PERFMON 15 -#define IRQ_IOP32X_CORE_PMU 16 -#define IRQ_IOP32X_BIU_ERR 17 -#define IRQ_IOP32X_ATU_ERR 18 -#define IRQ_IOP32X_MCU_ERR 19 -#define IRQ_IOP32X_DMA0_ERR 20 -#define IRQ_IOP32X_DMA1_ERR 21 -#define IRQ_IOP32X_AA_ERR 23 -#define IRQ_IOP32X_MSG_ERR 24 -#define IRQ_IOP32X_SSP 25 -#define IRQ_IOP32X_XINT0 27 -#define IRQ_IOP32X_XINT1 28 -#define IRQ_IOP32X_XINT2 29 -#define IRQ_IOP32X_XINT3 30 -#define IRQ_IOP32X_HPI 31 +#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0) +#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1) +#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2) +#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3) +#define IRQ_IOP32X_AA_EOT IOP_IRQ(6) +#define IRQ_IOP32X_AA_EOC IOP_IRQ(7) +#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8) +#define IRQ_IOP32X_TIMER0 IOP_IRQ(9) +#define IRQ_IOP32X_TIMER1 IOP_IRQ(10) +#define IRQ_IOP32X_I2C_0 IOP_IRQ(11) +#define IRQ_IOP32X_I2C_1 IOP_IRQ(12) +#define IRQ_IOP32X_MESSAGING IOP_IRQ(13) +#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14) +#define IRQ_IOP32X_PERFMON IOP_IRQ(15) +#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16) +#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17) +#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18) +#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19) +#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20) +#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21) +#define IRQ_IOP32X_AA_ERR IOP_IRQ(23) +#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24) +#define IRQ_IOP32X_SSP IOP_IRQ(25) +#define IRQ_IOP32X_XINT0 IOP_IRQ(27) +#define IRQ_IOP32X_XINT1 IOP_IRQ(28) +#define IRQ_IOP32X_XINT2 IOP_IRQ(29) +#define IRQ_IOP32X_XINT3 IOP_IRQ(30) +#define IRQ_IOP32X_HPI IOP_IRQ(31) #endif -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel