From: Bjorn Helgaas <helgaas@kernel.org>
To: qizhong cheng <qizhong.cheng@mediatek.com>
Cc: "Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyiński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"Chuanjia Liu" <chuanjia.liu@mediatek.com>,
"Jiey Yang" <ot_jiey.yang@mediatek.com>
Subject: Re: [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable
Date: Mon, 6 Dec 2021 19:53:23 -0600 [thread overview]
Message-ID: <20211207015323.GA26237@bhelgaas> (raw)
In-Reply-To: <20211104062144.31453-1-qizhong.cheng@mediatek.com>
On Thu, Nov 04, 2021 at 02:21:44PM +0800, qizhong cheng wrote:
> Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and
> 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
> be delayed 100ms (TPVPERL) for the power and clock to become stable.
Thanks for the spec references.
s/setctions/sections/
> Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..b32acbac8084 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> */
> writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
>
> + /*
> + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal)
> + * and 2.2.1 (Initial Power-Up (G3 to S0)).
> + * The deassertion of PERST# should be delayed 100ms (TPVPERL)
> + * for the power and clock to become stable.
s/setctions/sections/ again. Otherwise we'll have a typo-fixing patch
eventually.
Please also rewrap into one paragraph.
> + */
> + msleep(100);
> +
> /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> val = readl(port->base + PCIE_RST_CTRL);
> val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> --
> 2.25.1
>
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next prev parent reply other threads:[~2021-12-07 1:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 6:21 [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable qizhong cheng
2021-11-04 11:41 ` Pali Rohár
2021-12-06 11:35 ` Lorenzo Pieralisi
2021-12-07 1:53 ` Bjorn Helgaas [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-12-07 6:05 qizhong cheng
2021-12-07 12:16 ` Bjorn Helgaas
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