From: Thierry Reding <thierry.reding@gmail.com>
To: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Jon Hunter <jonathanh@nvidia.com>,
linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] arm64: tegra: Drop arm,armv8-pmuv3 compatible string
Date: Tue, 7 Dec 2021 16:07:46 +0100 [thread overview]
Message-ID: <20211207150746.444478-3-thierry.reding@gmail.com> (raw)
In-Reply-To: <20211207150746.444478-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific compatible strings instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++--
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 5f8132884be0..eb739ffbdfce 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1892,14 +1892,14 @@ L2_A57: l2-cache1 {
};
pmu_denver {
- compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+ compatible = "nvidia,denver-pmu";
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&denver_0 &denver_1>;
};
pmu_a57 {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 8d29b7fdb044..a0025b1c425f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2687,7 +2687,7 @@ l3c: l3-cache {
};
pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "nvidia,carmel-pmu";
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
--
2.33.1
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next prev parent reply other threads:[~2021-12-07 15:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-07 15:07 [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs Thierry Reding
2021-12-07 15:07 ` [PATCH 2/3] arm64: perf: Support " Thierry Reding
2021-12-07 16:03 ` Mark Rutland
2021-12-08 14:36 ` Thierry Reding
2021-12-14 12:33 ` Will Deacon
2021-12-14 14:28 ` Thierry Reding
2021-12-14 14:36 ` Will Deacon
2021-12-07 15:07 ` Thierry Reding [this message]
2021-12-08 13:44 ` [PATCH 1/3] dt-bindings: arm: pmu: Document " Rob Herring
2021-12-08 14:41 ` Thierry Reding
2021-12-08 17:06 ` Rob Herring
2021-12-08 18:51 ` Rob Herring
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