From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89CE2C433F5 for ; Thu, 9 Dec 2021 22:32:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NdqJpYyvzCBEakU620BgglxhD7STAJwwKmFsj6OQ0FU=; b=XYJGqx2/KGR67j iTFm/9DXTA3ZvWHogNcvaWl7vvtPfHuNNU058L1uvC/Pp651/Ft9bC0XN/8d3oKbmu+m1j5PSjdqU we3z1rb4d3mOq/wHYquKDrllLyF5JdzOTivd4Hgyr+dbGCcp31i1oQrA4kloSacAP0saY9/YUKr6Z DItTUWqiaqYL4r+SJKVN0NK5V4JCqGyIOouWpiGLzjV90c7M/CKNb+u8epy+eMdM+a5KORselci5M A81O+gYJ/ATxdo51rrcYgJm1Jsyrg1wsQGoIwWVn/vIffJBWy7yrYUT5a3QU4q6+m0UsHjJfv721f FZR8CbnVOApce84V+KcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvRwX-000HK4-P7; Thu, 09 Dec 2021 22:31:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvRwU-000HIo-Ei for linux-arm-kernel@lists.infradead.org; Thu, 09 Dec 2021 22:31:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E4DBD6E; Thu, 9 Dec 2021 14:31:09 -0800 (PST) Received: from bogus (unknown [10.57.33.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 936383F73D; Thu, 9 Dec 2021 14:31:06 -0800 (PST) Date: Thu, 9 Dec 2021 22:31:03 +0000 From: Sudeep Holla To: Rob Herring Cc: "Peng Fan (OSS)" , Shawn Guo , Sudeep Holla , Sascha Hauer , Sascha Hauer , Fabio Estevam , NXP Linux Team , Philipp Zabel , Lucas Stach , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel , "linux-kernel@vger.kernel.org" , Peng Fan Subject: Re: [PATCH 3/3] arm64: dts: imx8qxp: add cache info Message-ID: <20211209223103.br2scdg2j6gpfnpl@bogus> References: <20211112062604.3485365-1-peng.fan@oss.nxp.com> <20211112062604.3485365-4-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211209_143110_584548_FFB2764B X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 09, 2021 at 04:15:09PM -0600, Rob Herring wrote: > On Fri, Nov 12, 2021 at 12:27 AM Peng Fan (OSS) wrote: > > > > From: Peng Fan > > > > i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache > > - Icache is 2-way set associative > > - Dcache is 4-way set associative > > - L2cache is 8-way set associative > > - Line size are 64bytes > > > > Signed-off-by: Peng Fan > > --- > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > index 617618edf77e..dbec7c106e0b 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > @@ -58,6 +58,12 @@ A35_0: cpu@0 { > > compatible = "arm,cortex-a35"; > > reg = <0x0 0x0>; > > enable-method = "psci"; > > + i-cache-size = <0x8000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <256>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > Why do you need all this for the L1? Isn't it discoverable with cache > ID registers? > No, not after the following: Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") which removed ID register based cache probing and we now expect to obtain the same via DT/ACPI unfortunately. -- Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel