From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2453C433F5 for ; Fri, 10 Dec 2021 15:15:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=XV8i1nwNdCgKe698LQHShjOwJryU3qLkiuveb4q84iY=; b=aCIr8Z1n+9fpd4 LK/DbeANEucR2XVXaSNov0vtEMJ7OTX9dz9GRr6DEldsjs+WniRDLAoP7NoR/uOW/SqvNfeXDOMKS CcKLE/YBo/cIbjHS5Xn62/U4Qlo03j31ya+F7mCnA6H4lLzyWjKE+D3Ms3TNG7y4I1qSom8+paZnu etJwGHsxQb3RQhSvlE+3g2kE1Sm9EliVLaLHoPJDQ8cccvZDg0FuWAE7SGv3eYG+gJQIqcmV1pget UgjQos/LAlNHFlHS5p/ZYEU322+xURuNlEB9rJieOCFaxip2zn8oA8CM+tYj+cuA/CeJVaCIQIOjR lnfM6l/UmCjOKWlDrfgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhbN-002LIF-K6; Fri, 10 Dec 2021 15:14:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhbH-002LFL-Uw for linux-arm-kernel@lists.infradead.org; Fri, 10 Dec 2021 15:14:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 906A1106F; Fri, 10 Dec 2021 07:14:16 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A9EF03F5A1; Fri, 10 Dec 2021 07:14:15 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: boqun.feng@gmail.com, catalin.marinas@arm.com, mark.rutland@arm.com, peterz@infradead.org, will@kernel.org Subject: [PATCH 0/5] arm64: atomics: cleanups and codegen improvements Date: Fri, 10 Dec 2021 15:14:05 +0000 Message-Id: <20211210151410.2782645-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_071420_128311_5D3A9ACB X-CRM114-Status: UNSURE ( 8.07 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org While looking at Peter's recent refcount rework, I spotted that we have some unfortunate code generation for the LSE atomics. Due to a combination of assembly constraints and manipulation performed in assembly which the compiler has no visibilty of, the compiler ends up generating unnecessary register shuffling and redundant manipulation. This series (based on v5.16-rc4) attempts to improve this by improving the constraints, and moving value manipulation to C where the compiler can perofrm a number of optimizations. This also has the benefit of simplifying the implementation and deleting 100+ lines of code. This is purely a cleanup and optimization; there should be no functional change as a result of the series. I've pushed the series out to my arm64/atomics/improvements branch: https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h=arm64/atomics/improvements git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git arm64/atomics/improvements For comparison, using GCC 11.1.0 to compile the following code: | s64 example64_fetch_and(s64 i, atomic64_t *v) | { | return __lse_atomic64_fetch_and(i, v); | } | | s64 example64_fetch_and_f(atomic64_t *v) | { | return __lse_atomic64_fetch_and(0xf, v); | } | | s64 example64_fetch_sub(s64 i, atomic64_t *v) | { | return __lse_atomic64_fetch_sub(i, v); | } | | s64 example64_fetch_sub_f(atomic64_t *v) | { | return __lse_atomic64_fetch_sub(0xf, v); | } | | s64 example64_sub_return(s64 i, atomic64_t *v) | { | return __lse_atomic64_sub_return(i, v); | } | | s64 example64_sub_return_f(atomic64_t *v) | { | return __lse_atomic64_sub_return(0xf, v); | } Before this series: | 0000000000000000 : | 0: aa2003e0 mvn x0, x0 | 4: f8e01020 ldclral x0, x0, [x1] | 8: d65f03c0 ret | c: d503201f nop | | 0000000000000010 : | 10: aa0003e2 mov x2, x0 | 14: d28001e1 mov x1, #0xf // #15 | 18: aa0103e0 mov x0, x1 | 1c: aa2003e0 mvn x0, x0 | 20: f8e01040 ldclral x0, x0, [x2] | 24: d65f03c0 ret | 28: d503201f nop | 2c: d503201f nop | | 0000000000000030 : | 30: cb0003e0 neg x0, x0 | 34: f8e00020 ldaddal x0, x0, [x1] | 38: d65f03c0 ret | 3c: d503201f nop | | 0000000000000040 : | 40: aa0003e2 mov x2, x0 | 44: d28001e1 mov x1, #0xf // #15 | 48: aa0103e0 mov x0, x1 | 4c: cb0003e0 neg x0, x0 | 50: f8e00040 ldaddal x0, x0, [x2] | 54: d65f03c0 ret | 58: d503201f nop | 5c: d503201f nop | | 0000000000000060 : | 60: cb0003e0 neg x0, x0 | 64: f8e00022 ldaddal x0, x2, [x1] | 68: 8b020000 add x0, x0, x2 | 6c: d65f03c0 ret | | 0000000000000070 : | 70: aa0003e2 mov x2, x0 | 74: d28001e1 mov x1, #0xf // #15 | 78: aa0103e0 mov x0, x1 | 7c: cb0003e0 neg x0, x0 | 80: f8e00041 ldaddal x0, x1, [x2] | 84: 8b010000 add x0, x0, x1 | 88: d65f03c0 ret | 8c: d503201f nop After this series: | 0000000000000000 : | 0: aa2003e0 mvn x0, x0 | 4: f8e01020 ldclral x0, x0, [x1] | 8: d65f03c0 ret | c: d503201f nop | | 0000000000000010 : | 10: 928001e1 mov x1, #0xfffffffffffffff0 // #-16 | 14: f8e11001 ldclral x1, x1, [x0] | 18: aa0103e0 mov x0, x1 | 1c: d65f03c0 ret | | 0000000000000020 : | 20: cb0003e0 neg x0, x0 | 24: f8e00020 ldaddal x0, x0, [x1] | 28: d65f03c0 ret | 2c: d503201f nop | | 0000000000000030 : | 30: 928001c1 mov x1, #0xfffffffffffffff1 // #-15 | 34: f8e10001 ldaddal x1, x1, [x0] | 38: aa0103e0 mov x0, x1 | 3c: d65f03c0 ret | | 0000000000000040 : | 40: cb0003e2 neg x2, x0 | 44: f8e20022 ldaddal x2, x2, [x1] | 48: cb000040 sub x0, x2, x0 | 4c: d65f03c0 ret | | 0000000000000050 : | 50: 928001c1 mov x1, #0xfffffffffffffff1 // #-15 | 54: f8e10001 ldaddal x1, x1, [x0] | 58: d1003c20 sub x0, x1, #0xf | 5c: d65f03c0 ret Thanks, Mark. Mark Rutland (5): arm64: atomics: format whitespace consistently arm64: atomics lse: define SUBs in terms of ADDs arm64: atomics: lse: define ANDs in terms of ANDNOTs arm64: atomics: lse: improve constraints for simple ops arm64: atomics: lse: define RETURN ops in terms of FETCH ops arch/arm64/include/asm/atomic_ll_sc.h | 86 ++++---- arch/arm64/include/asm/atomic_lse.h | 270 ++++++++------------------ 2 files changed, 126 insertions(+), 230 deletions(-) -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel