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From: Maxime Ripard <maxime@cerno.tech>
To: Guillaume Ranquet <granquet@baylibre.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Markus Schneider-Pargmann <msp@baylibre.com>,
	kernel test robot <lkp@intel.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 7/7] drm/mediatek: Add mt8195 DisplayPort driver
Date: Mon, 13 Dec 2021 17:54:22 +0100	[thread overview]
Message-ID: <20211213165422.54n3oh72tjcb3a67@houat> (raw)
In-Reply-To: <CABnWg9tcWdfPQwNtFhqVZxCriT848fy42VHoQZs3X2UmL4LYSA@mail.gmail.com>


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On Thu, Dec 02, 2021 at 06:48:12AM -0800, Guillaume Ranquet wrote:
> Hi,
> 
> Quoting Maxime Ripard (2021-11-25 15:30:34)
> > On Wed, Nov 24, 2021 at 01:45:21PM +0000, Guillaume Ranquet wrote:
> > > Hi,
> > > Thanks for all your input, really appreciated.
> > >
> > > Quoting Maxime Ripard (2021-11-16 15:51:12)
> > > > Hi,
> > > >
> > > > On Mon, Nov 15, 2021 at 09:33:52AM -0500, Guillaume Ranquet wrote:
> > > > > Quoting Maxime Ripard (2021-11-15 11:11:29)
> > > > > > > The driver creates a child device for the phy. The child device will
> > > > > > > never exist without the parent being active. As they are sharing a
> > > > > > > register range, the parent passes a regmap pointer to the child so that
> > > > > > > both can work with the same register range. The phy driver sets device
> > > > > > > data that is read by the parent to get the phy device that can be used
> > > > > > > to control the phy properties.
> > > > > >
> > > > > > If the PHY is in the same register space than the DP controller, why do
> > > > > > you need a separate PHY driver in the first place?
> > > > >
> > > > > This has been asked by Chun-Kuang Hu in a previous revision of the series:
> > > > >
> > > > > https://lore.kernel.org/linux-mediatek/CAAOTY_-+T-wRCH2yw2XSm=ZbaBbqBQ4EqpU2P0TF90gAWQeRsg@mail.gmail.com/
> > > >
> > > > It's a bit of a circular argument though :)
> > > >
> > > > It's a separate phy driver because it needs to go through another
> > > > maintainer's tree, but it needs to go through another maintainer's tree
> > > > because it's a separate phy driver.
> > > >
> > > > It doesn't explain why it needs to be a separate phy driver? Why can't
> > > > the phy setup be done directly in the DP driver, if it's essentially a
> > > > single device?
> > > >
> > > > That being said, usually what those kind of questions mean is that
> > > > you're missing a comment or something in the commit log to provide that
> > > > context in the first place, so it would be great to add that context
> > > > here.
> > > >
> > > > And it will avoid the situation we're now in where multiple reviewers
> > > > ask the same questions over and over again :)
> > > >
> > > At first I didn't understand your reply, then I realized I gave you
> > > the wrong link...
> > > my bad! I'm struggling a bit with mail reviews, but I'll get there eventually.
> > >
> > > The driver and phy were a single driver until v2 of this patch series
> > > and the phy setup
> > > was done directly in the driver (single driver, single C file).
> > > Here's the relevant link to the discussion between Chun-Kuang and Markus
> > >
> > > https://lore.kernel.org/linux-mediatek/CAAOTY__cJMqcAieEraJ2sz4gi0Zs-aiNXz38_x7dPQea6HvYEg@mail.gmail.com/#t
> > >
> > > I'll try to find a way to make it clearer for v7.
> >
> > OK, it makes sense then :)
> >
> > There's something weird though: the devices definitely look like they're
> > in a separate register range, yet you mention a regmap to handle the
> > shared register range. That range doesn't seem described anywhere in the
> > device tree though? What is it for?
>
> My understanding is that 0x1000 to 0x1fff controls the phy
> functionalities and 0x2000 to 0x4fff controls "non-phy"
> functionalities. And you are right, there's no description of that in
> the device tree whatsoever. The ranges are in the same actual device
> and thus it has been decided to not have dt-bindings for the phy
> device.

Sure, that last part makes sense, but then I'm not sure why you don't
have the full register range in the device node you have in the DT?

> The phy driver is a child of the DP driver that we register using
> platform_device_register_data() and we pass along the same regmap as
> the DP driver in its platform data.

Especially if it's used by something, it should be described in the DT
somewhere.

Maxime

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  reply	other threads:[~2021-12-13 16:56 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-10 13:06 [PATCH v6 0/7] drm/mediatek: Add mt8195 DisplayPort driver Guillaume Ranquet
2021-11-10 13:06 ` [PATCH v6 1/7] dt-bindings: mediatek,dpi: Add DP_INTF compatible Guillaume Ranquet
2021-11-10 13:06 ` [PATCH v6 2/7] dt-bindings: mediatek,dp: Add Display Port binding Guillaume Ranquet
2021-11-10 19:44   ` [PATCH v6 2/7] dt-bindings: mediatek, dp: " Rob Herring
2021-11-10 13:06 ` [PATCH v6 5/7] drm/mediatek: dpi: Add dpintf support Guillaume Ranquet
2021-11-26 10:22   ` AngeloGioacchino Del Regno
2021-11-26 10:23   ` AngeloGioacchino Del Regno
2021-12-15 20:14   ` Matthias Brugger
2021-11-10 13:06 ` [PATCH v6 6/7] phy: phy-mtk-dp: Add driver for DP phy Guillaume Ranquet
2021-11-13  7:48   ` Chunfeng Yun
2021-11-24 14:37     ` Guillaume Ranquet
     [not found] ` <20211110130623.20553-8-granquet@baylibre.com>
     [not found]   ` <20211115101129.lyxxmb6i7paaonwi@gilmour>
     [not found]     ` <CABnWg9tNPGZSi1RLqF5+Qs1GHtynyVoOzAyw+i9mPRYEoByk8g@mail.gmail.com>
2021-11-16 14:51       ` [PATCH v6 7/7] drm/mediatek: Add mt8195 DisplayPort driver Maxime Ripard
2021-11-24 13:45         ` Guillaume Ranquet
2021-11-25 14:30           ` Maxime Ripard
2021-12-02 14:48             ` Guillaume Ranquet
2021-12-13 16:54               ` Maxime Ripard [this message]
2021-12-15 15:03                 ` Guillaume Ranquet
2021-12-15 15:15                   ` Maxime Ripard
2021-12-15 16:02                     ` Guillaume Ranquet
2021-12-15 16:06                       ` Maxime Ripard
2021-11-25 15:27   ` Chun-Kuang Hu
2021-12-02 15:31     ` Guillaume Ranquet
2021-12-15 14:13       ` Guillaume Ranquet
2021-12-09  6:29   ` Hsin-Yi Wang
2021-12-15 13:59     ` Guillaume Ranquet
2021-12-10 10:17   ` AngeloGioacchino Del Regno
2021-12-15 13:56     ` Guillaume Ranquet

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