From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F25E3C433F5 for ; Mon, 13 Dec 2021 19:30:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/zyjlJICI1QlJKhtDZhe6hd40Foux1lEzlu99iO2Vro=; b=njDoefjudakOPG bCndcuVKDyNbz40a6CdUGdgoseXYUbybjPY21DOA7fbAGX1VRKwErDPuSCmF9zlqkJACk16RvCzAQ oWon44H6TMqMWarwjtp6BQgfIGwLKjJ/vGgD63/8jJbMsDX3gqzUGJC5txSKc1e8dGyX2aU7/Ceaa ZubC3MhZUFKJSoNif8VcrgjM83We2U1XJpbqdbK9W5hzzGnrGi7H7SG7cqnRuQT67qLNsvl8Pq+P6 /D7p6S2ABhBkJWpyUQUIPLn/0sO8zrPcuk4cNm4O7E1k+XVpRA3AeIIuaz7Mb0NVw1EOq0ikbAXI9 1md+C/pnXTQRsBSZB8Iw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwr17-00B9QM-5o; Mon, 13 Dec 2021 19:29:45 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwr13-00B9PR-QI for linux-arm-kernel@lists.infradead.org; Mon, 13 Dec 2021 19:29:43 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5570960FF4; Mon, 13 Dec 2021 19:29:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC0B2C34602; Mon, 13 Dec 2021 19:29:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639423780; bh=tA9jQAROuLpEyJtdkTzLSJOmpyapiuulNdruJ4oSfNU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=J8cCxYeDSdPMETtu0+8mA57GFV0RcQNetaMiSkTRVUo/0D8atDvhvMEwEi/flr4TZ kunTT4jZO5hDO1ipxnQGcjc1GYvdnhHcQSXpO/JpLTiD+pbq0C7AOwp+vqHXUAz+qi 6zXhc0JX6Z9trRRn0YeFxUnAT1mRpXZhTjXAnRWURox7lgD7QW36fy1KhcCB1FPzeN hf9fZgyxW1pCUujfODj4c6pzk06iaHkPmDPVhN4sJuneQAcFOrC+7pF6E8QcceU4fc 0F0xCs1cyPWxuFWMfM9QorZPpaGdLatzw/4Bo6KXseH+u17xr2Sfz+x6mlYc1Bi4rY 6tTEfMdenpt1Q== Date: Mon, 13 Dec 2021 19:29:36 +0000 From: Will Deacon To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, boqun.feng@gmail.com, catalin.marinas@arm.com, peterz@infradead.org Subject: Re: [PATCH 3/5] arm64: atomics: lse: define ANDs in terms of ANDNOTs Message-ID: <20211213192935.GC12868@willie-the-truck> References: <20211210151410.2782645-1-mark.rutland@arm.com> <20211210151410.2782645-4-mark.rutland@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211210151410.2782645-4-mark.rutland@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211213_112941_916909_80E5C180 X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 10, 2021 at 03:14:08PM +0000, Mark Rutland wrote: > The FEAT_LSE atomic instructions include atomic bit-clear instructions > (`ldclr*` and `stclr*`) which can be used to directly implement ANDNOT > operations. Each AND op is implemented as a copy of the corresponding > ANDNOT op with a leading `mvn` instruction to apply a bitwise NOT to the > `i` argument. > > As the compiler has no visibility of the `mvn`, this leads to less than > optimal code generation when generating `i` into a register. For > example, __lse_atomic_fetch_and(0xf, v) can be compiled to: > > mov w1, #0xf > mvn w1, w1 > ldclral w1, w1, [x2] > > This patch improves this by replacing the `mvn` with NOT in C before the > inline assembly block, e.g. > > i = ~i; > > This allows the compiler to generate `i` into a register more optimally, > e.g. > > mov w1, #0xfffffff0 > ldclral w1, w1, [x2] > > With this change the assembly for each AND op is identical to the > corresponding ANDNOT op (including barriers and clobbers), so I've > removed the inline assembly and rewritten each AND op in terms of the > corresponding ANDNOT op, e.g. > > | static inline void __lse_atomic_and(int i, atomic_t *v) > | { > | return __lse_atomic_andnot(~i, v); > | } > > This is intended as an optimization and cleanup. > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Cc: Boqun Feng > Cc: Catalin Marinas > Cc: Peter Zijlstra > Cc: Will Deacon > --- > arch/arm64/include/asm/atomic_lse.h | 34 ++++------------------------- > 1 file changed, 4 insertions(+), 30 deletions(-) Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel