From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5435EC433FE for ; Mon, 13 Dec 2021 19:41:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o44EM0BFsGO7PXDFtcKcJFMgFrRoUhoTH25jle0y9eA=; b=saWBtqQc918xNG vJmk75FWDgR4wzIAJ++gI058XbmZN+37R54dJfxiiwztSglsweJFuHaQvx54oZ2iYFdeWBw46kedb uOCwuWDzez/MsB5OvoJ5o6X4itgDFeON5TGfXgnJaYgHh/VEDzfXDDD3fVlU9N9Nf9dDhfOo+ymOf QSbzQ/XiEKbzDIsOFaqer5MO0FimPBkUClIPN0Ww+S5bDcsarBT6Cpmm7eaiaoiReTffrCBL1a6C0 kkOx6Gi38JgTnGnVIzahWQ55cmHEDJQ5Fy5wfEbeb4xy1wqeG4PxakBa35qpQtFH3Cn8wIX1gXm4T 25sqEr9Eq4Lihdj3QAXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwrBY-00BB7M-Dt; Mon, 13 Dec 2021 19:40:32 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mwrBV-00BB6U-0I for linux-arm-kernel@lists.infradead.org; Mon, 13 Dec 2021 19:40:30 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 872F5611D4; Mon, 13 Dec 2021 19:40:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D521DC34602; Mon, 13 Dec 2021 19:40:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639424427; bh=3S2y6PC9f+u51UkQQkGyKpnJFR02OiMzobrFXo889JE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=U0aEMvzbz0aXOPZbZXnk/C32wB6X1us465eidAXOaNRC/m0e/ppcOSwt9gZO29Fr9 s5ElRXE0/M6HYsf/KStU8MIbp+e7qb4ghzuD4Pydi7V6sBrsZ9J0aD0Oj+48XsKjBC lnh/64rgTGBaT2owCAyyvKc5xULk05s/dg1V6rd/pojbuxM1dRUgbcSYo7RxRnyNqj hgHjvm/3KR+C10wn15v+WlEYDn5MuUC/x1aEdmd9Yg45JiQc3rr+LeQaXtDIs0r9hI 6N0bcdvWVN5oZuPTrNOl4Y7Vr1FMtZdEl5FxVflZoF1isfCmTn+7aIGtD+jC2XnCpa zztD174gRZmCg== Date: Mon, 13 Dec 2021 19:40:23 +0000 From: Will Deacon To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, boqun.feng@gmail.com, catalin.marinas@arm.com, peterz@infradead.org Subject: Re: [PATCH 4/5] arm64: atomics: lse: improve constraints for simple ops Message-ID: <20211213194022.GD12868@willie-the-truck> References: <20211210151410.2782645-1-mark.rutland@arm.com> <20211210151410.2782645-5-mark.rutland@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211210151410.2782645-5-mark.rutland@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211213_114029_157933_A6B76D57 X-CRM114-Status: GOOD ( 27.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 10, 2021 at 03:14:09PM +0000, Mark Rutland wrote: > We have overly conservative assembly constraints for the basic FEAT_LSE > atomic instructions, and using more accurate and permissive constraints > will allow for better code generation. > > The FEAT_LSE basic atomic instructions have come in two forms: > > LD{op}{order}{size} , , [] > ST{op}{order}{size} , [] > > The ST* forms are aliases of the LD* forms where: > > ST{op}{order}{size} , [] > Is: > LD{op}{order}{size} , XZR, [] > > For either form, both and are read but not written back to, > and is written with the original value of the memory location. > Where ( == ) or ( == ), is written *after* the > other register value(s) are consumed. There are no UNPREDICTABLE or > CONSTRAINED UNPREDICTABLE behaviours when any pair of , , or > are the same register. > > Our current inline assembly always uses == , treating this > register as both an input and an output (using a '+r' constraint). This > forces the compiler to do some unnecessary register shuffling and/or > redundant value generation. > > For example, the compiler cannot reuse the value, and currently GCC > 11.1.0 will compile: > > __lse_atomic_add(1, a); > __lse_atomic_add(1, b); > __lse_atomic_add(1, c); > > As: > > mov w3, #0x1 > mov w4, w3 > stadd w4, [x0] > mov w0, w3 > stadd w0, [x1] > stadd w3, [x2] > > We can improve this with more accurate constraints, separating and > , where is an input-only register ('r'), and is an > output-only value ('=r'). As is written back after is > consumed, it does not need to be earlyclobber ('=&r'), leaving the > compiler free to use the same register for both and where this > is desirable. > > At the same time, the redundant 'r' constraint for `v` is removed, as > the `+Q` constraint is sufficient. > > With this change, the above example becomes: > > mov w3, #0x1 > stadd w3, [x0] > stadd w3, [x1] > stadd w3, [x2] > > I've made this change for the non-value-returning and FETCH ops. The > RETURN ops have a multi-instruction sequence for which we cannot use the > same constraints, and a subsequent patch will rewrite hte RETURN ops in > terms of the FETCH ops, relying on the ability for the compiler to reuse > the value. > > This is intended as an optimization. > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Cc: Boqun Feng > Cc: Catalin Marinas > Cc: Peter Zijlstra > Cc: Will Deacon > --- > arch/arm64/include/asm/atomic_lse.h | 30 +++++++++++++++++------------ > 1 file changed, 18 insertions(+), 12 deletions(-) Makes sense to me. I'm not sure _why_ the current constraints are so weird; maybe a hangover from when we patched them inline? Anywho: Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel