From: Rob Herring <robh@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
James Morse <james.morse@arm.com>,
Jeremy Linton <jeremy.linton@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Sudeep Holla <sudeep.holla@arm.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
devicetree@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: [PATCH 1/6] cacheinfo: Allow for >32-bit cache 'id'
Date: Thu, 16 Dec 2021 17:31:20 -0600 [thread overview]
Message-ID: <20211216233125.1130793-2-robh@kernel.org> (raw)
In-Reply-To: <20211216233125.1130793-1-robh@kernel.org>
In preparation to set the cache 'id' based on the CPU h/w ids which are
64-bit on arm64, allow for a 64-bit bit 'id' value. The only case that
needs this is arm64, so unsigned long is sufficient.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/base/cacheinfo.c | 8 +++++++-
include/linux/cacheinfo.h | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index dad296229161..66d10bdb863b 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -366,13 +366,19 @@ static ssize_t file_name##_show(struct device *dev, \
return sysfs_emit(buf, "%u\n", this_leaf->object); \
}
-show_one(id, id);
show_one(level, level);
show_one(coherency_line_size, coherency_line_size);
show_one(number_of_sets, number_of_sets);
show_one(physical_line_partition, physical_line_partition);
show_one(ways_of_associativity, ways_of_associativity);
+static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct cacheinfo *this_leaf = dev_get_drvdata(dev);
+
+ return sysfs_emit(buf, "%lu\n", this_leaf->id);
+}
+
static ssize_t size_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2f909ed084c6..b2e7f3e40204 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -48,7 +48,7 @@ extern unsigned int coherency_max_size;
* keeping, the remaining members form the core properties of the cache
*/
struct cacheinfo {
- unsigned int id;
+ unsigned long id;
enum cache_type type;
unsigned int level;
unsigned int coherency_line_size;
--
2.32.0
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next prev parent reply other threads:[~2021-12-16 23:32 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 23:31 [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Rob Herring
2021-12-16 23:31 ` Rob Herring [this message]
2021-12-16 23:31 ` [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-12-17 16:57 ` Robin Murphy
2021-12-17 18:14 ` Rob Herring
2021-12-17 19:03 ` Sudeep Holla
2021-12-17 19:08 ` Sudeep Holla
2021-12-17 19:26 ` Rob Herring
2021-12-17 20:28 ` Jeremy Linton
2021-12-17 19:08 ` Robin Murphy
2021-12-17 19:35 ` Rob Herring
2021-12-17 20:22 ` Jeremy Linton
2021-12-17 21:13 ` Robin Murphy
2021-12-16 23:31 ` [PATCH 3/6] cacheinfo: Add cpu_affinity_map to store affinity for all CPUs Rob Herring
2021-12-16 23:31 ` [PATCH 4/6] ACPI / PPTT: Populate the cacheinfo.cpu_affinity_map Rob Herring
2021-12-16 23:31 ` [PATCH 5/6] cacheinfo: Use cpu_affinity_map for populating shared_cpu_map Rob Herring
2021-12-16 23:31 ` [PATCH 6/6] cacheinfo: Add cacheinfo_get_cache_affinity() function Rob Herring
2021-12-21 9:31 ` [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Greg Kroah-Hartman
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