From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53C67C433F5 for ; Wed, 22 Dec 2021 03:17:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=oac8exCeNg0P8AXEV5WwLJY4KYPz3kGhTd7EQ/RXnAA=; b=ba1VmZYPHCJAMg t9Mv4sHL3C++wRJb1UIkijDGy9K5WeeDBUmp54elSNGD1ZINbyhIKa6CeBAAx7mac8jp/gm0plEVl uuR7enM9DApzEvB3b/HgV53++ezM92fLCiW0D1+dBFvCygzdzPuRg7jcKpICjxJ/8iSOnYtJ8QaRj jox8wTi4AWpxfm8WtWsMs+TRq7zhVqKg2VTqyZpEIJN8PJOIQyHHCNPywK/K6z9sIfJG5yjo2wed+ jL3iObn5+q04IvvTDLlMOJ9DVs9f4TzYElNmFNs7DZElWjqslGAupc33KxfrJH3fogEcFSEVvBVXd UfHBGmLEY+D/yaNRJFIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mzs6c-0094bf-4S; Wed, 22 Dec 2021 03:15:54 +0000 Received: from out28-50.mail.aliyun.com ([115.124.28.50]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mzs6Y-0094a4-96 for linux-arm-kernel@lists.infradead.org; Wed, 22 Dec 2021 03:15:52 +0000 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1217135|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0561819-0.000317092-0.943501; FP=7011064724060272356|1|1|5|0|-1|-1|-1; HT=ay29a033018047199; MF=michael@allwinnertech.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.MMifRmp_1640142945; Received: from sunxibot.allwinnertech.com(mailfrom:michael@allwinnertech.com fp:SMTPD_---.MMifRmp_1640142945) by smtp.aliyun-inc.com(10.147.42.135); Wed, 22 Dec 2021 11:15:45 +0800 From: Michael Wu To: ulf.hansson@linaro.org, mripard@kernel.org, wens@csie.org, samuel@sholland.org, andre.przywara@arm.com Cc: jernej.skrabec@gmail.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Wu Subject: [PATCH 2/3] mmc:sunxi-mmc:fix clock division for timing mode Date: Wed, 22 Dec 2021 11:15:21 +0800 Message-Id: <20211222031521.34170-1-michael@allwinnertech.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211221_191550_512351_C5FD7784 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When use new timings,all speed mode requires a doubled module clock if speed mode is ddr,requires a four times module clock When use old timings,only 8 bit ddr requires a doubled module clock Signed-off-by: Michael Wu --- drivers/mmc/host/sunxi-mmc.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index afeefead6501..7b47ec453fb6 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -774,20 +774,23 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, if (!ios->clock) return 0; - /* - * Under the old timing mode, 8 bit DDR requires the module - * clock to be double the card clock. Under the new timing - * mode, all DDR modes require a doubled module clock. - * - * We currently only support the standard MMC DDR52 mode. - * This block should be updated once support for other DDR - * modes is added. + /** + * When use new timings, all speed mode requires a doubled module clock. + * if speed mode is ddr, requires a four times module clock. + * When use old timings, only 8 bit ddr requires a doubled module clock. */ - if (ios->timing == MMC_TIMING_MMC_DDR52 && - (host->use_new_timings || - ios->bus_width == MMC_BUS_WIDTH_8)) { - div = 2; + if (host->use_new_timings) { clock <<= 1; + if (ios->timing == MMC_TIMING_MMC_DDR52) { + div = 2; + clock <<= 1; + } + } else { + if (ios->timing == MMC_TIMING_MMC_DDR52 && + (ios->bus_width == MMC_BUS_WIDTH_8)) { + div = 2; + clock <<= 1; + } } if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { -- 2.29.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel