From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DE98C433EF for ; Fri, 7 Jan 2022 16:02:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YOR1V1dP6uiESwiHPQjnKILsPH6cRm3QPskhaaIhtjY=; b=WaQedjkPdh7hk1 Uu95h3lC4iHlgnmmGnOdWw68tn5NvxWNeQdVvqGChNaayU8XdDe5pN8ZKYMmml0NijiHCqWorNpKv 5x+eYzadPglZmDga5vMMRLO0up3SI6js/pjfUg6I/6T977aK/xuPTfdsahxRZZ/5bRrPHcPzu9th0 472IPQ9gCuELdGxkmJI7hy2gOhDSNdPqXwmcdIcICM47pSkfHiN/ifmtcnftxfq6LquLUB6YRv+hg d4zOQ99+mGjccuvJdbLwjnCxls9qaEJKduIN2t6eTXaaU95jYeAKjnACIcwETklcFAdzVPATyFxT1 55mU8t12HzGE4qLi5v6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5rgN-004Zb6-4j; Fri, 07 Jan 2022 16:01:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5rfz-004ZTR-4U for linux-arm-kernel@lists.infradead.org; Fri, 07 Jan 2022 16:01:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF3DA13D5; Fri, 7 Jan 2022 08:01:09 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B74743F66F; Fri, 7 Jan 2022 08:01:08 -0800 (PST) From: Andre Przywara To: Will Deacon , Catalin Marinas Cc: Marc Zyngier , Mark Rutland , Jonathan Corbet , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: booting.rst: Cover Armv8-R64 Date: Fri, 7 Jan 2022 16:00:56 +0000 Message-Id: <20220107160056.322141-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107160056.322141-1-andre.przywara@arm.com> References: <20220107160056.322141-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_080111_255040_C961AD70 X-CRM114-Status: GOOD ( 12.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is a new revision of the ARMv8-R architecture [1], which optionally introduces kernel compatibility - by introducing an MMU into EL1 and EL0. Linux can run on such an implementation, if it is entered in EL1 and VMSA is both implemented and enabled for that exception level. Clarify our kernel boot protocol to make this an officially supported mode of operation, but also limit the expectations about running in secure state (which is the only security state in v8-R). Also we heavily rely on the Virtual Memory System Architecture (VMSA), make this explicit in the text, as this allows to cover v8-R64 as well. [1] https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Andre Przywara --- Documentation/arm64/booting.rst | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 07cb34ed4200..99fab4d7e7ad 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -167,8 +167,13 @@ Before jumping into the kernel, the following conditions must be met: All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, IRQ and FIQ). - The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order - to have access to the virtualisation extensions), or in EL1. + If the CPU supports two security states, Linux must be entered in + non-secure state, either in EL2 (RECOMMENDED in order to have access + to the virtualisation extensions) or in EL1. + If the CPU only supports a single security state, Linux can be run even + when this single state is "secure". + The exception level the kernel is entered in must support the VMSA + memory model. - Caches, MMUs -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel