From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E823C433F5 for ; Fri, 7 Jan 2022 21:57:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UHcceGuPSxUKfX/Rqt8zPmqg5HmkTau8ubNZEf8CLOs=; b=efGcosi6Jg+hax MpJic2KhhzExHM8dljnhW3jRGNDw12uhauARo/hYgR72kWT+f/Bzry7UV/F6I5DQtnVCeOoHGjhsE miEdiJePY8OCN3TOPdsiOW2F/E4aW0tvQNx6Q7PTNNvoz98+UJMfM/L9Sx7xpIFxoHgZJ8ijMJwSe vZLdwy0lRBzr1JjqVuzjQvPMHhB6po7DxPMb/jFWTRyA3Y1IkALE9ZeBrd5s1VtMkBchNSU1f6epR QNIxFhKybQGtSbY73h5yLf1AwnWaeplkR62EInhZDSJSvI9p6mTuAbNXeH3jmlfD8OEN84MiIBe8E rMiIGIDC6UUZiSRBT4lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5xDH-005JXr-2k; Fri, 07 Jan 2022 21:55:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5xDD-005JW8-Uf for linux-arm-kernel@lists.infradead.org; Fri, 07 Jan 2022 21:55:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1304A113E; Fri, 7 Jan 2022 13:55:48 -0800 (PST) Received: from localhost.localdomain (unknown [10.122.33.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A0643F66F; Fri, 7 Jan 2022 13:55:47 -0800 (PST) From: Chase Conklin To: maz@kernel.org Cc: alexandru.elisei@arm.com, andre.przywara@arm.com, christoffer.dall@arm.com, gankulkarni@os.amperecomputing.com, haibo.xu@linaro.org, james.morse@arm.com, jintack@cs.columbia.edu, kernel-team@android.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Subject: Re: [PATCH v5 08/69] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Date: Fri, 7 Jan 2022 15:54:01 -0600 Message-Id: <20220107215401.61828-1-chase.conklin@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211129200150.351436-9-maz@kernel.org> References: <20211129200150.351436-9-maz@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_135552_081785_9E1F76B4 X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Mon Nov 29 15:00:49 EST 2021, Marc Zyngier wrote: > From: Christoffer Dall > > Reset the VCPU with PSTATE.M = EL2h when the nested virtualization > feature is enabled on the VCPU. > > Signed-off-by: Christoffer Dall > [maz: rework register reset not to use empty data structures] > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/reset.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > index 426bd7fbc3fd..38a7182819fb 100644 > --- a/arch/arm64/kvm/reset.c > +++ b/arch/arm64/kvm/reset.c > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > #include > > /* Maximum phys_shift supported for any VM on this host */ > @@ -38,6 +39,9 @@ static u32 kvm_ipa_limit; > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > PSR_F_BIT | PSR_D_BIT) > > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > + PSR_F_BIT | PSR_D_BIT) > + > #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > PSR_AA32_I_BIT | PSR_AA32_F_BIT) > > @@ -176,8 +180,8 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) > return false; > > - /* MTE is incompatible with AArch32 */ > - if (kvm_has_mte(vcpu->kvm) && is32bit) > + /* MTE and NV are incompatible with AArch32 */ > + if ((kvm_has_mte(vcpu->kvm) || nested_virt_in_use(vcpu)) && is32bit) > return false; Should something similar be done for SVE? I see from the ID register emulation that SVE is hidden from the guest but there isn't anything in kvm_vcpu_enable_sve() that checks if NV is in use. That means it's possible to have both nested_virt_in_use(vcpu) and vcpu_has_sve(vcpu) be true simultaneously. If that happens, the FPSIMD fixup can get confused /* * Don't handle SVE traps for non-SVE vcpus here. This * includes NV guests for the time being. */ if (!sve_guest && (esr_ec != ESR_ELx_EC_FP_ASIMD || guest_hyp_fpsimd_traps_enabled(vcpu))) return false; and incorrectly restore the wrong context instead of forwarding a FPSIMD trap to the guest hypervisor. Thanks, Chase > /* Check that the vcpus are either all 32bit or all 64bit */ > @@ -255,6 +259,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) > default: > if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { > pstate = VCPU_RESET_PSTATE_SVC; > + } else if (nested_virt_in_use(vcpu)) { > + pstate = VCPU_RESET_PSTATE_EL2; > } else { > pstate = VCPU_RESET_PSTATE_EL1; > } > -- > 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel