From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C92BCC433F5 for ; Tue, 11 Jan 2022 14:42:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/eI9yOGY7280jSbWk2VipzX/J2nT3EOEZKkE5FH00Mk=; b=a0osYAUF/NeXyq ywau/LEiPQcXb2foqD/oVSocAuhglQt3Q4Zv8TMIqdTVTA13wWLwIpGf+9gkBp14Spvsm5DtUiAy4 4leLtKweOikyOZGoFTGBm1y46mCj2hjBlNJad/dNcBpmq8Im7qecUvc5cvzFVHOS+jILjiiKlrQiY y/kW3yqu7se8CgpxQULMk/FEk7tN4gecd2LosG5uM51MQMTrENEk8Ooz/DEE0DJEjzfzo9KL9Xuzs o5Mvto1M1ifszKXgSp/yltRYQsa0et99M8ZOWoGohcswVFP2GAEBmABOvzvqmRBl49V5Lb5siXqWo r92uhxo+jSvteHu4/M9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7IKX-00GaMO-8j; Tue, 11 Jan 2022 14:40:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7IKT-00GaL8-Kj for linux-arm-kernel@lists.infradead.org; Tue, 11 Jan 2022 14:40:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D07751FB; Tue, 11 Jan 2022 06:40:50 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 464E03F774; Tue, 11 Jan 2022 06:40:50 -0800 (PST) Date: Tue, 11 Jan 2022 14:40:48 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com, Wei.Chen@arm.com Subject: Re: [bootwrapper PATCH 02/13] Add bit-field macros Message-ID: <20220111144048.2675076e@donnerap.cambridge.arm.com> In-Reply-To: <20220111130653.2331827-3-mark.rutland@arm.com> References: <20220111130653.2331827-1-mark.rutland@arm.com> <20220111130653.2331827-3-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220111_064053_778512_FAEEECD9 X-CRM114-Status: GOOD ( 22.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 11 Jan 2022 13:06:42 +0000 Mark Rutland wrote: Hi Mark, > Arm architectural documentation typically defines bit-fields as > `[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be > helpful if we could define fields in the same way. > > Add helpers so that we can do so, along with helper to extract/insert > bit-field values. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > --- > include/bits.h | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 include/bits.h > > diff --git a/include/bits.h b/include/bits.h > new file mode 100644 > index 0000000..8824a38 > --- /dev/null > +++ b/include/bits.h > @@ -0,0 +1,33 @@ > +/* > + * include/bits.h - helpers for bit-field definitions. > + * > + * Copyright (C) 2021 ARM Limited. All rights reserved. > + * > + * Use of this source code is governed by a BSD-style license that can be > + * found in the LICENSE.txt file. > + */ > +#ifndef __BITS_H > +#define __BITS_H > + > +#ifdef __ASSEMBLY__ > +#define UL(x) x > +#define ULL(x) x > +#else > +#define UL(x) x##UL > +#define ULL(x) x##ULL > +#endif > + > +#define BITS(msb, lsb) \ The kernel uses GENMASK() for this, should we follow suit here? Both U-Boot and Trusted Firmware decided to do so, so I consider this some kind of agreed naming for bitmask generation these days. > +((~ULL(0) >> (63 - msb)) & (~ULL(0) << lsb)) > + > +#define BIT(b) BITS(b, b) > + > +#define BITS_LSB(bits) (__builtin_ffsll(bits) - 1) Shall there be some comment explaining the functionality and arguments? Or maybe use "mask" instead of the more ambiguous "bits" name here? TBH I needed to read the implementation of the next macro to understand what it does. > + > +#define BITS_EXTRACT(val, bits) \ Same here, having BITS_EXTRACT(val, mask) looks more readable to me. Cheers, Andre > + (((val) & (bits)) >> BITS_LSB(bits)) > + > +#define BITS_INSERT(bits, val) \ > + (((val) << BITS_LSB(bits)) & (bits)) > + > +#endif _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel