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From: Bjorn Helgaas <helgaas@kernel.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: "Rob Herring" <robh@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Tiezhu Yang" <yangtiezhu@loongson.cn>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Ray Jui" <rjui@broadcom.com>,
	"Scott Branden" <sbranden@broadcom.com>,
	bcm-kernel-feedback-list@broadcom.com,
	linux-arm-kernel@lists.infradead.org,
	linux-pci <linux-pci@vger.kernel.org>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH 19/19] PCI: Set bridge map_irq and swizzle_irq to default functions
Date: Wed, 12 Jan 2022 15:10:39 -0600	[thread overview]
Message-ID: <20220112211039.GA281591@bhelgaas> (raw)
In-Reply-To: <84d849b5-9386-4db5-87fe-34de3d6c487b@www.fastmail.com>

On Wed, Jan 12, 2022 at 08:08:45PM +0000, Jiaxun Yang wrote:
> 在2022年1月12日一月 下午3:19,Bjorn Helgaas写道:
> > On Wed, Jan 12, 2022 at 12:57:44PM +0000, Jiaxun Yang wrote:
> >> 在2022年1月11日一月 下午9:46,Bjorn Helgaas写道:
> >> > [-cc many, +cc iproc, loongson, tegra maintainers]
> [...]
> > I see these:
> >
> >   Documentation/devicetree/bindings/pci/loongson.yaml
> >   arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> >
> > which makes me think there are Loongson systems with DT.  Are there
> > some Loongson systems with DT and some legacy ones without?
> 
> Actually all present MIPS/Loongson systems are legacy and we just
> built-in DTs in kernel and select which one to use at boot time. 

So I guess you know enough about what platform it is to select which
DT to use, but you don't know enough to know the I8259 routing?

If you *could* select a DT that described the I8259 routing, I guess
maybe you could select a matching DT or update a DT in-place?

> > The only driver I see is drivers/pci/controller/pci-loongson.c.
> > Is that used for all Loongson system?  It unconditionally uses
> > ->map_irq = loongson_map_irq().
> 
> Yes, it's used among all Loongson systems.  For system using LS7A
> PCH the IRQ mapping is fixed so we just programmed it in DT. For
> RS780E we use this routine to read PCI_INTERRUPT_LINE to select
> which I8259 IRQ to use.
> 
> > loongson_map_irq() reads PCI_INTERRUPT_LINE; I think that depends
> > on firmware having previously programmed it, right?
> 
> I'm unclear about what did firmware do but as AMD RS780E is used in
> x86 PCs as well it should be the same way.

PCI devices don't use the value in PCI_INTERRUPT_LINE, and the spec
doesn't define a default value.  It's only for use by software.

I'm pretty sure that on ACPI x86, we don't depend on
PCI_INTERRUPT_LINE except for things like quirks.

I think the ACPI MADT and _PRT are supposed to contain all the INTx
routing information we need.  Obviously this isn't an ACPI system.
I'm just making the point that it *should* be possible to remove this
dependency on firmware if we can identify the specific platform (which
determines the I8259 routing).

Bjorn

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  reply	other threads:[~2022-01-12 21:12 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-22  2:24 [PATCH 00/19] PCI: Another round of host clean-ups Rob Herring
2020-07-22  2:24 ` [PATCH 01/19] PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS Rob Herring
2020-07-22  2:24 ` [PATCH 02/19] PCI: Set default bridge parent device Rob Herring
2020-07-22  2:24 ` [PATCH 03/19] PCI: Drop unnecessary zeroing of bridge fields Rob Herring
2020-07-22  2:24 ` [PATCH 04/19] PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus Rob Herring
2020-07-22  2:25 ` [PATCH 05/19] PCI: designware: " Rob Herring
2020-07-22  2:25 ` [PATCH 06/19] PCI: mobiveil: " Rob Herring
2020-07-22  2:25 ` [PATCH 07/19] PCI: xilinx-nwl: " Rob Herring
2020-07-22  2:25 ` [PATCH 08/19] PCI: xilinx: " Rob Herring
2020-07-22  2:25 ` [PATCH 09/19] PCI: rockchip: " Rob Herring
2020-07-22  2:25 ` [PATCH 10/19] PCI: rcar: " Rob Herring
2020-07-22  2:25 ` [PATCH 11/19] PCI: Move setting pci_host_bridge.busnr out of host drivers Rob Herring
2020-07-23 15:26   ` Rob Herring
2020-07-23 16:21     ` Lorenzo Pieralisi
2020-07-23 16:55       ` Rob Herring
2020-07-22  2:25 ` [PATCH 12/19] PCI: cadence: Use bridge resources for outbound window setup Rob Herring
2020-07-22  2:25 ` [PATCH 13/19] PCI: cadence: Remove private bus number and range storage Rob Herring
2020-07-22  2:25 ` [PATCH 14/19] PCI: rcar: Use devm_pci_alloc_host_bridge() Rob Herring
2020-07-22  2:25 ` [PATCH 15/19] PCI: rcar: Use struct pci_host_bridge.windows list directly Rob Herring
2020-07-22  2:25 ` [PATCH 16/19] PCI: of: Reduce missing non-prefetchable memory region to a warning Rob Herring
2020-07-22  2:25 ` [PATCH 17/19] PCI: rcar-gen2: Convert to use modern host bridge probe functions Rob Herring
2020-08-04 12:12   ` Geert Uytterhoeven
2020-08-04 15:13     ` Rob Herring
2020-07-22  2:25 ` [PATCH 18/19] PCI: Move DT resource setup into devm_pci_alloc_host_bridge() Rob Herring
2020-07-22  2:25 ` [PATCH 19/19] PCI: Set bridge map_irq and swizzle_irq to default functions Rob Herring
2022-01-11 21:46   ` Bjorn Helgaas
2022-01-12 12:57     ` Jiaxun Yang
2022-01-12 15:19       ` Bjorn Helgaas
2022-01-12 20:08         ` Jiaxun Yang
2022-01-12 21:10           ` Bjorn Helgaas [this message]
2022-01-13 17:44             ` Jiaxun Yang
2022-01-12 15:09     ` Rob Herring
2022-01-12 15:32       ` Bjorn Helgaas
2022-01-29 22:34     ` Maciej W. Rozycki
2020-07-22 21:06 ` [PATCH 00/19] PCI: Another round of host clean-ups Bjorn Helgaas
2020-07-23 10:39 ` Lorenzo Pieralisi

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