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Fri, 14 Jan 2022 04:24:15 -0500 (EST) Date: Fri, 14 Jan 2022 10:24:13 +0100 From: Maxime Ripard To: Evgeny Boger Cc: linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Jernej Skrabec , Yangtao Li , Icenowy Zheng , andre.przywara@arm.com Subject: Re: [PATCH v2 1/1] phy: sun4i-usb: fix phy write on H3 and newer Message-ID: <20220114092413.exs7miua5n42kpbp@houat> References: <20220111165153.63632-1-boger@wirenboard.com> <20220111165153.63632-2-boger@wirenboard.com> <20220112084223.j5nm4ennfv7f6ekt@houat> <1e13f894-6900-15a8-66ea-f5e4d65bf822@wirenboard.com> MIME-Version: 1.0 In-Reply-To: <1e13f894-6900-15a8-66ea-f5e4d65bf822@wirenboard.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220114_012417_593315_CC77BF5F X-CRM114-Status: GOOD ( 41.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8002741341997108190==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============8002741341997108190== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="mjxfyaaz7lvw5h4s" Content-Disposition: inline --mjxfyaaz7lvw5h4s Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Jan 12, 2022 at 11:59:31AM +0300, Evgeny Boger wrote: > Hi Maxime! > 12.01.2022 11:42, Maxime Ripard =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > Hi, > >=20 > > On Tue, Jan 11, 2022 at 07:51:53PM +0300, Evgeny Boger wrote: > > > We noticed that USB hosts won't reliably enumerate USB HS (480Mb/s) d= evices > > > in our custom A40i-based design. What we observe is that after several > > > attempts USB device would fail to enumerate on EHCI port (HS) and wil= l be > > > enumerated instead on OHCI (FS, 12Mb/s) only: > > >=20 > > > [ 6.368009] usb 1-1: new high-speed USB device number 5 using ehci= -platform > > > [ 6.818008] usb 1-1: device not accepting address 5, error -71 > > > [ 6.823868] usb usb1-port1: unable to enumerate USB device > > > [ 7.308013] usb 3-1: new full-speed USB device number 2 using ohci= -platform > > > [ 7.575045] usb 3-1: not running at top speed; connect to a high s= peed hub > > >=20 > > > On some boards one of the ports would work in high-speed mode, but > > > on most of the boards all three USB ports would only work in FS mode. > > >=20 > > > At the same time, USB work flawlessly in high-speed mode in vendor ke= rnel. > > >=20 > > > Looking for the differences in USB code, we found the issue with USB = PHY > > > register initialization. Basically, USB PHY driver sets a couple of > > > internal undocumented PHY registers to the predefined constants. Thes= e PHY > > > registers are accessed in a very (and I mean VERY) weird way by shift= ing > > > register addresses and values bit-by-bit. This access method was slig= htly > > > changed starting from H3 SoC, according to the BSP source for differe= nt > > > SoCs. > > >=20 > > > As a result, mainline PHY driver won't set these PHY registers proper= ly > > > resulting in unreliable enumeration in high-speed mode. > > >=20 > > > We don't know whether this issue will result in broken HS mode on all > > > affected SoCs or instead the A40i is an unfortunate exception. What we > > > indeed verified, is that BSPs for all affected SoCs write these regis= ters > > > properly while mainline kernel don't. We also were able to reproduce = the > > > USB issue on a couple of A40i boards from other vendors, so we are pr= etty > > > sure these registers have to always be properly set, regardlress of > > > a hardware layout. > > >=20 > > > The proposed patch is tested on A40i-based Wiren Board 7 building > > > automation controller. More details are below. > > >=20 > > > On older SoCs (prior to H3) PHY register are accessed by manipulating > > > the common register for all PHYs. PHY index is specified by pulsing > > > usbc bit. > > >=20 > > > Newer SoCs leave the access procedure mostly unchanged, the > > > difference being that the latch registers are separate for each PHY. > > >=20 > > > Additionally, accessing USB PHY registers is only possible if phy0 is > > > routed to musb IP instead of HCI. > > >=20 > > > Introduce phy_reg_access_v2 cfg flag for H3 (H2+, H5), > > > R40 (V40, A40i, T3), V3s (V3, S3) and A64 SoCs. > > >=20 > > > On A83t, H6, H616, T507 and probably on more recent hardware, > > > these PHY registers are not used in vendor BSP. > > > So don't set v2 flag for these even newer SoCs as a precaution. > > >=20 > > > Signed-off-by: Evgeny Boger > > This should probably be sent to stable, and have a Fixes tag? >=20 > well, phy register writes never worked on H3 SoC and newer, so there is no > specific commit which broke it. So nothing to put to Fixes: tag. If anything, it should be the patch that introduces the H3 support? > I'm not sure it qualifies for stable too. Citing guidelines: >=20 > >It must be obviously correct and tested >=20 > I was only able to test it on handful of A40i boards and on one A20 board >=20 > >It must fix a real bug that bothers people >=20 > this bug for certain bothers *us*, but our users won't benefit from porti= ng > this fix to stable. > I didn't find reports on this bug from other people. > I think unfortunately not many people are using mainline kernel on these > SoCs. Yeah, it makes sense then, thanks! Maxime --mjxfyaaz7lvw5h4s Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYeFBPQAKCRDj7w1vZxhR xYS0AQCZH5g291Vf2fh1VjfLr3vqIRsPww5ycNA8W3GTdoPpZQEAtqWnkzS5SzZH 5mZ8LMaS1EHLqo5JB8tknu7J2mvJ5AU= =KxDc -----END PGP SIGNATURE----- --mjxfyaaz7lvw5h4s-- --===============8002741341997108190== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============8002741341997108190==--