From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CD93C433EF for ; Fri, 14 Jan 2022 10:59:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WLiL+I68+rdEy11yHz5wQ+9v+9FyYM0zixhKzdlGV3U=; b=EwXC8WxFalOqa7 BrDxqgTs5xwJowYV+OO282/G2/eIZlscW73sU9KvF9FFczAr1D5vN+1anJ/GQb0tb7j5yE9bUVigH ia49nxustxhhkFIF9/lZiHRWJe9iec69M2UJNv6LHKnJa2f+TURqb6Yi36eInOXl2eTBjlc1qnHQY f+G9ENyDDWPpf0FT6NuUGnj6pfO4B087S8naJLI1Crm6hN7s4KYUsFJLnT+n+7ct9f1PqpldEDux0 HVPu73r44skZBg/O4An309O2L9rhB06viI8mp2kawXowdumt8lRXmouP0jIm5Mjy8Gc8OGGkUkf64 koZgI8XN13Ao2TztMgEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8KHT-008oPR-5I; Fri, 14 Jan 2022 10:58:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8KGb-008o3R-QI for linux-arm-kernel@lists.infradead.org; Fri, 14 Jan 2022 10:57:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0990CED1; Fri, 14 Jan 2022 02:57:09 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 08EF43F766; Fri, 14 Jan 2022 02:57:07 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: [bootwrapper PATCH v2 04/13] aarch32: add coprocessor accessors Date: Fri, 14 Jan 2022 10:56:44 +0000 Message-Id: <20220114105653.3003399-5-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220114105653.3003399-1-mark.rutland@arm.com> References: <20220114105653.3003399-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220114_025709_992298_3AAC60C0 X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We open code the use of mrc/mcr for specific registers, which is somewhat tedious. Add macros to do this generically, along with a helper to extract a specific register field. Existing C usage is converted to the new helpers, and register definitions moved to a common location. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland --- arch/aarch32/include/asm/cpu.h | 45 ++++++++++++++++++++----------- arch/aarch32/include/asm/gic-v3.h | 6 +++-- 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index 105cae5..d691c7b 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -9,9 +9,13 @@ #ifndef __ASM_AARCH32_CPU_H #define __ASM_AARCH32_CPU_H +#include + #define MPIDR_ID_BITS 0x00ffffff #define MPIDR_INVALID (-1) +#define ID_PFR1_GIC BITS(31, 28) + /* Only RES1 bits and CP15 barriers for the kernel */ #define HSCTLR_KERNEL (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 | 1 << 11 | 3 << 4) #define SCTLR_KERNEL (3 << 22 | 1 << 11 | 1 << 5 | 3 << 4) @@ -40,32 +44,43 @@ #define sevl() asm volatile ("sev" : : : "memory") #endif -static inline unsigned long read_mpidr(void) -{ - unsigned long mpidr; +#define MPIDR "p15, 0, %0, c0, c0, 5" +#define ID_PFR1 "p15, 0, %0, c0, c1, 1" +#define ICIALLU "p15, 0, %0, c7, c5, 0" - asm volatile ("mrc p15, 0, %0, c0, c0, 5\n" : "=r" (mpidr)); - return mpidr & MPIDR_ID_BITS; -} +#define ICC_SRE "p15, 6, %0, c12, c12, 5" +#define ICC_CTLR "p15, 6, %0, c12, c12, 4" -static inline uint32_t read_id_pfr1(void) -{ - uint32_t val; +#define mrc(reg) \ +({ \ + unsigned long __mrc_val; \ + asm volatile("mrc " reg : "=r" (__mrc_val)); \ + __mrc_val; \ +}) - asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r" (val)); - return val; +#define mcr(reg, val) \ +do { \ + unsigned long __mcr_val = val; \ + asm volatile("mcr " reg : : "r" (__mcr_val)); \ +} while (0) + + +#define mrc_field(reg, field) \ + BITS_EXTRACT(mrc(reg), (reg##_##field)) + +static inline unsigned long read_mpidr(void) +{ + return mrc(MPIDR) & MPIDR_ID_BITS; } static inline void iciallu(void) { - uint32_t val = 0; - - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (val)); + mcr(ICIALLU, 0); } static inline int has_gicv3_sysreg(void) { - return !!((read_id_pfr1() >> 28) & 0xf); + return !!mrc_field(ID_PFR1, GIC); } #endif /* __ASSEMBLY__ */ diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index 65f38de..b28136a 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -9,14 +9,16 @@ #ifndef __ASM_AARCH32_GICV3_H #define __ASM_AARCH32_GICV3_H +#include + static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val)); + mcr(ICC_SRE, val); } static inline void gic_write_icc_ctlr(uint32_t val) { - asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); + mcr(ICC_CTLR, val); } #endif -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel