From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67288C433F5 for ; Mon, 17 Jan 2022 14:53:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tn4nIw7rdBaeYtxh7P3OpH1ZLkAfRZRiiEo4HpF3SKY=; b=WLvoFBP9HAJ0vb hRk3OGIoxRAjm65hXqFfjEAOHuPt8ZhoYhugquj7FwIvfvR1rbnuRHzY/Hpzn/ndOKegFG+fQr/YY EH4kYOZvaiU50p+8ymoGFxZP16Xgzu9qDopx4izVcO/Y3xz+xtH7S1B4g3+kkq1lc2ZTbwvoi8GyF pfGhUqmsjsR41Embg5SSphoe2NcU79vEW+ODWL24P0fmnioxxtZxxkptxUPc9UX1sRUTwJPLmwh5z /xf1fRWfORusWOTEiUXZR6XMlagVbthCJCzi4BniLpHKbobim1w1A9awd3HAMk4GyVtDxNxkKCbY9 ioer6BBywm4sxeAQgzHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9TMv-00FFFT-7V; Mon, 17 Jan 2022 14:52:25 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9TMr-00FFEw-Vl for linux-arm-kernel@lists.infradead.org; Mon, 17 Jan 2022 14:52:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 328A91FB; Mon, 17 Jan 2022 06:52:20 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 41B2A3F766; Mon, 17 Jan 2022 06:52:19 -0800 (PST) Date: Mon, 17 Jan 2022 14:52:16 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: Re: [bootwrapper PATCH v2 10/13] aarch32: move the bulk of Secure PL1 initialization to C Message-ID: <20220117145216.76bc664d@donnerap.cambridge.arm.com> In-Reply-To: <20220114105653.3003399-11-mark.rutland@arm.com> References: <20220114105653.3003399-1-mark.rutland@arm.com> <20220114105653.3003399-11-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220117_065222_147969_24279989 X-CRM114-Status: GOOD ( 17.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 14 Jan 2022 10:56:50 +0000 Mark Rutland wrote: Hi, > The majority of state that we initialize at Secure PL1 is necessary for > code at lower PLs to function, but isnt' necessary for the boot-wrapper > itself. Given that, it would be better to write this in C where it can > be written mode clearly, and where it will be possible to add > logging/debug logic. > > This patch migrates the AArch32 Secure PL1 initialization to C. > > There should be no functional change as a result of this patch. I compared the removed assembly code against to added C code, and also checked the register bits against the ARMv7 ARM. Everything checks out, so: > Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/aarch32/boot.S | 11 +---------- > arch/aarch32/include/asm/cpu.h | 9 +++++++++ > arch/aarch32/init.c | 12 ++++++++++++ > 3 files changed, 22 insertions(+), 10 deletions(-) > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > index ee073ea..820957b 100644 > --- a/arch/aarch32/boot.S > +++ b/arch/aarch32/boot.S > @@ -63,16 +63,7 @@ _monitor: > /* Move the stack to Monitor mode*/ > mrs sp, sp_svc > > - /* Setup secure registers and devices */ > - mov r0, #1 @ Non-secure lower level > - orr r0, #(1 << 8) @ HVC enable > - mcr p15, 0, r0, c1, c1, 0 @ SCR > - > - mov r0, #(1 << 10 | 1 << 11) @ Enable NS access to CPACR > - mcr p15, 0, r0, c1, c1, 2 @ NSACR > - > - ldr r0, =COUNTER_FREQ > - mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ > + bl cpu_init_secure_pl1 > > bl cpu_init_bootwrapper > > diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h > index aa72204..c1bce9a 100644 > --- a/arch/aarch32/include/asm/cpu.h > +++ b/arch/aarch32/include/asm/cpu.h > @@ -30,6 +30,11 @@ > #define PSR_I (1 << 7) > #define PSR_A (1 << 8) > > +#define SCR_NS BIT(0) > +#define SCR_HCE BIT(8) > + > +#define NSACR_CP10 BIT(10) > +#define NSACR_CP11 BIT(11) > > #define SPSR_KERNEL (PSR_A | PSR_I | PSR_F | PSR_HYP) > > @@ -55,11 +60,15 @@ static inline unsigned long read_cpsr(void) > > #define MPIDR "p15, 0, %0, c0, c0, 5" > #define ID_PFR1 "p15, 0, %0, c0, c1, 1" > +#define SCR "p15, 0, %0, c1, c1, 0" > +#define NSACR "p15, 0, %0, c1, c1, 2" > #define ICIALLU "p15, 0, %0, c7, c5, 0" > > #define ICC_SRE "p15, 6, %0, c12, c12, 5" > #define ICC_CTLR "p15, 6, %0, c12, c12, 4" > > +#define CNTFRQ "p15, 0, %0, c14, c0, 0" > + > #define mrc(reg) \ > ({ \ > unsigned long __mrc_val; \ > diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c > index b29ebb4..5b69dcd 100644 > --- a/arch/aarch32/init.c > +++ b/arch/aarch32/init.c > @@ -28,3 +28,15 @@ void announce_arch(void) > print_string(mode_string()); > print_string("\r\n"); > } > + > +void cpu_init_secure_pl1(void) > +{ > + unsigned long scr = SCR_NS | SCR_HCE; > + unsigned long nsacr = NSACR_CP10 | NSACR_CP11; > + > + mcr(SCR, scr); > + > + mcr(NSACR, nsacr); > + > + mcr(CNTFRQ, COUNTER_FREQ); > +} _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel