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From: "Pali Rohár" <pali@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Marek Behún" <kabel@kernel.org>,
	"Russell King" <rmk+kernel@armlinux.org.uk>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 08/11] PCI: mvebu: Use child_ops API
Date: Thu, 20 Jan 2022 17:55:22 +0100	[thread overview]
Message-ID: <20220120165522.v2xitzokcom4phmw@pali> (raw)
In-Reply-To: <YemSgTfl7NiTfcKc@robh.at.kernel.org>

On Thursday 20 January 2022 10:49:05 Rob Herring wrote:
> On Wed, Jan 12, 2022 at 04:18:11PM +0100, Pali Rohár wrote:
> > Split struct pci_ops between ops and child_ops. Member ops is used for
> > accessing PCIe Root Ports via pci-bridge-emul.c driver and child_ops for
> > accessing real PCIe cards.
> > 
> > There is no need to mix these two struct pci_ops into one as PCI core code
> > already provides separate callbacks via bridge->ops and bridge->child_ops.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> >  drivers/pci/controller/pci-mvebu.c | 82 ++++++++++++++++--------------
> >  1 file changed, 44 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> > index 9ea2f6a7c2b0..1e90ab888075 100644
> > --- a/drivers/pci/controller/pci-mvebu.c
> > +++ b/drivers/pci/controller/pci-mvebu.c
> > @@ -294,11 +294,29 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
> >  	mvebu_writel(port, mask, PCIE_MASK_OFF);
> >  }
> >  
> > -static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
> > -				 struct pci_bus *bus,
> > -				 u32 devfn, int where, int size, u32 *val)
> > +static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
> > +						    struct pci_bus *bus,
> > +						    int devfn);
> > +
> > +static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> > +				    int size, u32 *val)
> >  {
> > -	void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
> > +	struct mvebu_pcie *pcie = bus->sysdata;
> > +	struct mvebu_pcie_port *port;
> > +	void __iomem *conf_data;
> > +
> > +	port = mvebu_pcie_find_port(pcie, bus, devfn);
> > +	if (!port) {
> > +		*val = 0xffffffff;
> > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > +	}
> > +
> > +	if (!mvebu_pcie_link_up(port)) {
> > +		*val = 0xffffffff;
> > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > +	}
> > +
> > +	conf_data = port->base + PCIE_CONF_DATA_OFF;
> >  
> >  	mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
> >  		     PCIE_CONF_ADDR_OFF);
> > @@ -321,11 +339,21 @@ static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
> >  	return PCIBIOS_SUCCESSFUL;
> >  }
> >  
> > -static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
> > -				 struct pci_bus *bus,
> > -				 u32 devfn, int where, int size, u32 val)
> > +static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn,
> > +				    int where, int size, u32 val)
> >  {
> > -	void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
> > +	struct mvebu_pcie *pcie = bus->sysdata;
> > +	struct mvebu_pcie_port *port;
> > +	void __iomem *conf_data;
> > +
> 
> > +	port = mvebu_pcie_find_port(pcie, bus, devfn);
> > +	if (!port)
> > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > +	if (!mvebu_pcie_link_up(port))
> > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > +	conf_data = port->base + PCIE_CONF_DATA_OFF;
> 
> Again, the same setup code in read and write is a sign to use 
> .map_bus(). You can copy it from my version I pointed you to.
> 
> Rob

I'm planning to do other cleanup in followup patches. But there are too
many mvebu and aardvark patches on the list waiting, and I do not want
to send another batch.

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  reply	other threads:[~2022-01-20 16:56 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12  1:29   ` Rob Herring
2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-05 15:41   ` Rob Herring
2022-01-05 15:49     ` Pali Rohár
2022-01-12  1:43     ` Pali Rohár
2022-01-12 14:53       ` Rob Herring
2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12  1:30   ` Rob Herring
2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-01-06 15:28   ` Marc Zyngier
2022-01-06 15:44     ` Pali Rohár
2022-01-06 15:55       ` Marc Zyngier
2022-01-06 16:20         ` Pali Rohár
2022-01-06 16:27           ` Marc Zyngier
2022-01-06 17:20             ` Marek Behún
2022-01-06 17:31               ` Marc Zyngier
2022-01-07 11:50                 ` Pali Rohár
2022-01-07 18:53                   ` Marc Zyngier
2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-12 15:18   ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-12 15:18   ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-12 15:18   ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-12 15:18   ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 15:18   ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-20 17:09     ` Rob Herring
2022-01-20 17:19       ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-12 15:18   ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-12 15:18   ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-20 16:49     ` Rob Herring
2022-01-20 16:55       ` Pali Rohár [this message]
2022-01-20 18:40         ` Rob Herring
2022-01-12 15:18   ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 15:36     ` Marek Behún
2022-01-12 15:18   ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-02-11 17:19     ` Lorenzo Pieralisi
2022-02-11 17:52       ` Pali Rohár
2022-02-11 18:21         ` Lorenzo Pieralisi
2022-02-12 10:59           ` Marc Zyngier
2022-02-16 23:40         ` Pali Rohár
2022-02-22 10:21           ` Lorenzo Pieralisi
2022-02-22 10:51             ` Pali Rohár
2022-02-22 15:24               ` Lorenzo Pieralisi
2022-02-22 15:42                 ` Pali Rohár
2022-02-22 15:45                   ` Lorenzo Pieralisi
2022-02-22 15:55                     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-02-14 15:07     ` Gregory CLEMENT
2022-02-14 15:09       ` Pali Rohár
2022-02-14 15:26         ` Gregory CLEMENT
     [not found]           ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>
2022-02-15 10:48             ` Luís Mendes
2022-02-15 10:52               ` Pali Rohár
2022-02-18 21:53                 ` Luís Mendes
2022-02-19 13:36                   ` Pali Rohár
2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-11 18:01   ` Pali Rohár

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