From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AAC5C433EF for ; Tue, 25 Jan 2022 15:03:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=x1Y3X0fV70/+cVL90AOx7pFUk5cyVN5BLDyP4ZwQ8z0=; b=XzzLdd3dXiuPN7 l6OJEeNMVGp/7Y4Sw0AQEWesWtPuv2ccDOAIrj2F+Mt6IvvLU0YIh5abrcQZyIcoZuCtSpsTAzeA3 emQs0lcXj7+BV/NkuAkj5urFiM5NqcVLcqqpjGAcp6KqAoUQHOTAzwxh2ecCWOSl672LtZVzq8jt3 Tm5p//mYV0g2eYjqBBULkdtHD2LmP+Kt/5De6vzVxdK5+3VPTinfpixgq9jHu9yprUC6AF1H5VK1n BEFIMBy+cWilTQYzRThFyrdWwA/75tI0hWTCD2YgMWgf+XmrVg/RjuvE7/l9PCjWX493x1jG9mRJw WU6VrTN/wOphEhmL8W/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNKh-008F35-FM; Tue, 25 Jan 2022 15:02:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJg-008Ekp-PL for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03820D6E; Tue, 25 Jan 2022 07:01:03 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DB2BC3F793; Tue, 25 Jan 2022 07:01:01 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 00/15] Cleanups and improvements Date: Tue, 25 Jan 2022 15:00:42 +0000 Message-Id: <20220125150057.3936090-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070105_476104_8F0599D5 X-CRM114-Status: GOOD ( 17.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series reworks the aarch64 boot-wrapper, moving a fair amount of initialization code to C. This has a few benefits: 1) This makes the code more legible and easier to maintain. Current feature detection and system register configuration is written in assembly, requiring runs of *almost* identical blocks of assembly to read ID registers and conditionally initialize register values. This requires a bunch of labels (which are all named numerically), and all the magic numbers are hard coded, so this gets pretty painful to read: | mrs x1, id_aa64isar0_el1 | ubfx x1, x1, #24, #4 | cbz x1, 1f | | orr x0, x0, #(1 << 34) // TME enable | | 1: In C, it's much easier to add helpers which use mnemonics, which makes the code much easier to read, and avoids the need to manually allocate registers, etc: | if (mrs_field(ID_AA64ISAR0_EL1, TME)) | scr |= SCR_EL3_TME; This should make it easier to handle new architectural extensions (and/or architecture variants such as ARMv8-R) in future. 2) This allows for better diagnostics. Currently a mis-configured boot-wrapper is rather unforgiving, and provides no indication as to what might have gone wrong. By moving initialization to C, we can make use to the UART code to log diagnostic information, and we can more easily add additional error handling and conditional logic. This series adds diagnostic information and error handling that can be used to identify problems such as the boot-wrapper being launched at the wrong exception level: | Boot-wrapper v0.2 | Entered at EL2 | Memory layout: | [0000000080000000..0000000080001f90] => boot-wrapper | [000000008000fff8..0000000080010000] => mbox | [0000000080200000..00000000822af200] => kernel | [0000000088000000..0000000088002857] => dtb | | WARNING: PSCI could not be initialized. Boot may fail Originally I had planned for this to be a more expansive set of changes, unifying some early control-flow, fixing some latent bugs, and making the boot-wrapper dynamically handle being entered at any of EL{3,2,1} with automated selection of a suitable DT. As the series has already become pretty long, I'd like to get this preparatory cleanup out of the way first, and handle those cases with subsequent patches. If there are no objections I'll apply this by the end of this week. I've pushed the series to the `cleanup` branch in the boot-wrapper repo: https://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git/ git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git ... and it should apply cleanup atop the `master` branch. Since v1 [1]: * Add comments for bit-field macros * Use BIT() for *_RES1 definitions * Complete start_el3/start_no_el3 cleanup * Remove extraneous macro definition Since v2 [2]: * Accumulate tags * Rebase atop other recent patches * Correct ZCR_EL3.LEN initialization * Drop BITS_INSERT() * Split SCTLR_EL1 values used for AArch32 kernels * Add missing SCTLR_EL1 RES1 bits * Refactor print_ulong_hex() * Refactor PSCI arch initialization [1] https://lore.kernel.org/r/20220111130653.2331827-1-mark.rutland@arm.com/ [2] https://lore.kernel.org/r/20220114105653.3003399-1-mark.rutland@arm.com/ Thanks, Mark. Mark Rutland (15): aarch64: correct ZCR_EL3.LEN initialization aarch64: correct SCTLR_EL1_KERNEL for AA32 kernels Document entry requirements Add bit-field macros aarch64: add system register accessors aarch32: add coprocessor accessors aarch64: add mov_64 macro aarch64: initialize SCTLR_ELx for the boot-wrapper Rework common init C code Announce boot-wrapper mode / exception level aarch64: move the bulk of EL3 initialization to C aarch32: move the bulk of Secure PL1 initialization to C Announce locations of memory objects Rework bootmethod initialization Unify start_el3 & start_no_el3 Makefile.am | 7 +- arch/aarch32/boot.S | 33 ++++-- arch/aarch32/include/asm/cpu.h | 62 ++++++++--- arch/aarch32/include/asm/gic-v3.h | 6 +- arch/aarch32/init.c | 57 ++++++++++ arch/aarch32/psci.S | 16 +-- arch/aarch32/utils.S | 9 -- arch/aarch64/boot.S | 177 ++++++++++++------------------ arch/aarch64/common.S | 10 +- arch/aarch64/include/asm/cpu.h | 117 +++++++++++++++++--- arch/aarch64/include/asm/gic-v3.h | 10 +- arch/aarch64/init.c | 106 ++++++++++++++++++ arch/aarch64/psci.S | 22 +--- arch/aarch64/spin.S | 6 +- arch/aarch64/utils.S | 9 -- common/boot.c | 4 - common/init.c | 60 ++++++++++ common/platform.c | 45 +++++--- common/psci.c | 20 +++- include/bits.h | 66 +++++++++++ include/boot.h | 7 ++ include/platform.h | 20 ++++ model.lds.S | 20 +++- 23 files changed, 648 insertions(+), 241 deletions(-) create mode 100644 arch/aarch32/init.c create mode 100644 arch/aarch64/init.c create mode 100644 common/init.c create mode 100644 include/bits.h create mode 100644 include/platform.h -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel