From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6272CC433F5 for ; Tue, 25 Jan 2022 15:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bCHPIRPzMgfryn3EG3cgO/BEBdeA58rfzlEUzlmQCtY=; b=vXAIMzoSMxhPYh 4e60mwq9K+wQS6uARqywScHJ8QKcicLa0oM4DJEJcm+jsl6c3GBgwcX25PDBV4dpF4BNKmd/x8sv7 W9ADf+wn9mZLiND18Jwna86JIMm/h1tOGEeLjUvcaSMD8HJGM9Tt0vSLwkXFDCqFJ81yVPBGFNFvH KUClYLx+tdUKzwwQmfCL4BKYbjdy3wczLYl0qG0uA2zDtwvEdDXSgJ8+d1wdiIwb7KzPh6G95VrTm cpKB/YrRdfw0sKo9pK3NydFqGh4grWoGVKPzHFPr3fWHdOIEHFhjjb8jsJmLnZVVv+pQk4nAYr/G0 o/bsW9diAr13EtT/gByA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNS2-008IC9-GE; Tue, 25 Jan 2022 15:09:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK1-008EqA-Ut for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A47EFD6E; Tue, 25 Jan 2022 07:01:25 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8A0273F793; Tue, 25 Jan 2022 07:01:24 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 12/15] aarch32: move the bulk of Secure PL1 initialization to C Date: Tue, 25 Jan 2022 15:00:54 +0000 Message-Id: <20220125150057.3936090-13-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070126_079608_CB665418 X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The majority of state that we initialize at Secure PL1 is necessary for code at lower PLs to function, but isnt' necessary for the boot-wrapper itself. Given that, it would be better to write this in C where it can be written mode clearly, and where it will be possible to add logging/debug logic. This patch migrates the AArch32 Secure PL1 initialization to C. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 11 +---------- arch/aarch32/include/asm/cpu.h | 9 +++++++++ arch/aarch32/init.c | 12 ++++++++++++ 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index ee073ea..820957b 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -63,16 +63,7 @@ _monitor: /* Move the stack to Monitor mode*/ mrs sp, sp_svc - /* Setup secure registers and devices */ - mov r0, #1 @ Non-secure lower level - orr r0, #(1 << 8) @ HVC enable - mcr p15, 0, r0, c1, c1, 0 @ SCR - - mov r0, #(1 << 10 | 1 << 11) @ Enable NS access to CPACR - mcr p15, 0, r0, c1, c1, 2 @ NSACR - - ldr r0, =COUNTER_FREQ - mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ + bl cpu_init_secure_pl1 bl cpu_init_bootwrapper diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index aa72204..c1bce9a 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -30,6 +30,11 @@ #define PSR_I (1 << 7) #define PSR_A (1 << 8) +#define SCR_NS BIT(0) +#define SCR_HCE BIT(8) + +#define NSACR_CP10 BIT(10) +#define NSACR_CP11 BIT(11) #define SPSR_KERNEL (PSR_A | PSR_I | PSR_F | PSR_HYP) @@ -55,11 +60,15 @@ static inline unsigned long read_cpsr(void) #define MPIDR "p15, 0, %0, c0, c0, 5" #define ID_PFR1 "p15, 0, %0, c0, c1, 1" +#define SCR "p15, 0, %0, c1, c1, 0" +#define NSACR "p15, 0, %0, c1, c1, 2" #define ICIALLU "p15, 0, %0, c7, c5, 0" #define ICC_SRE "p15, 6, %0, c12, c12, 5" #define ICC_CTLR "p15, 6, %0, c12, c12, 4" +#define CNTFRQ "p15, 0, %0, c14, c0, 0" + #define mrc(reg) \ ({ \ unsigned long __mrc_val; \ diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index 785a428..7143c66 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -27,3 +27,15 @@ void announce_arch(void) print_string(mode_string()); print_string("\r\n"); } + +void cpu_init_secure_pl1(void) +{ + unsigned long scr = SCR_NS | SCR_HCE; + unsigned long nsacr = NSACR_CP10 | NSACR_CP11; + + mcr(SCR, scr); + + mcr(NSACR, nsacr); + + mcr(CNTFRQ, COUNTER_FREQ); +} -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel