From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40AF8C433F5 for ; Tue, 25 Jan 2022 15:04:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3A/wJ8wT335hxa/x9aX6HU+Fa/rb8nq44xefenK3THg=; b=jsJ1tRzUHFAeva a8vXZD5BzbQrZdRKdUL4sCTUXaHlvjbtdbOx6wkLU1zmMItg0UaZk4VIbYPl/svatoT2PKr5EcT89 iLN+rODLEWrdb4pFX6x4bX5STo2v4p9aRi3fojlT0DgFjDA8gfrxiGu8w9F4ybvjnfr4QjhvNVODU y+3YFC2XQbcxgOmQBpsZrAmdooMxayGl8ImXwtcjppHttg0DZc40lkSZE3BFDYl0EJ5C0bDxlRk9U 4d7GjjRl17OJrU3WVxWuzcsf5daRY1XO0NPGw9ZMwM63jUUWQKsut0+KePwmfgkg1YP2Q2LPYb7/I 43NRudyHFiiaEeZ4Ttvw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNKx-008F6l-9q; Tue, 25 Jan 2022 15:02:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJh-008Ele-RW for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D96FA101E; Tue, 25 Jan 2022 07:01:04 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BC8EE3F793; Tue, 25 Jan 2022 07:01:03 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 01/15] aarch64: correct ZCR_EL3.LEN initialization Date: Tue, 25 Jan 2022 15:00:43 +0000 Message-Id: <20220125150057.3936090-2-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070105_993132_EA5AC3D5 X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are RAZ/WI, likely so that in future these can be used to extend LEN without complicating the probing of the maximum available vector length. Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN field and the RAZ/WI bits. To match the architecture as documented, reduce this down to 0xf, only covering the bits currently allocated to the LEN field. We can extend this in future if the LEN field is widened. As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is used as a value rather than as a bit mask. Signed-off-by: Mark Rutland Cc: Andre Przywara Cc: Mark Brown --- arch/aarch64/boot.S | 2 +- arch/aarch64/include/asm/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 72c6b79..ee9ddaa 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -123,7 +123,7 @@ ASM_FUNC(_start) msr cptr_el3, x0 isb - mov x0, #ZCR_EL3_LEN_MASK // SVE: Enable full vector len + mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len msr ZCR_EL3, x0 // for EL2. 1: diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 63eb1c3..e3269b8 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,7 +30,7 @@ #define CPTR_EL3_EZ (1 << 8) #define ZCR_EL3 s3_6_c1_c2_0 -#define ZCR_EL3_LEN_MASK 0x1ff +#define ZCR_EL3_LEN_MAX 0xf #define SCTLR_EL1_CP15BEN (1 << 5) #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel