From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C7E7C3526D for ; Wed, 26 Jan 2022 15:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L/sG6cRFPLpVt6yTO+TbGju6s+bYIm9N3WzpuUb/eB8=; b=DvWfoo50YvEVNP 51WnqFhzlWA09djIliKfU0Qf9r02IFopMvARmV15HqzAkVvZkjUBJ/0zLXE+IvzVcsE915YoL4242 8ijEsZZj+emCXVa9fV87jZUaxLqchch72jJsUAlo2q36etOwpff/0n1n8oj0wnFcXoPCi0k9id7Mg brR5HTtLvFH1EcCTodCAbHnDh2xy//wmklkwdJKtLIdWSFUd8HPMp3Qe1EkCSWYPqhJC95xs9Jlv8 c47o5JuHJY9AzsePdp8l+pFnmFYMhN5lLTc8xu9DJus8HQrL7YaY0OnKkVerdSBueCSBfUh2LIMCR 5bkFzQkz73HSsoyVYWZA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCk3N-00CDLu-3y; Wed, 26 Jan 2022 15:17:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCjp5-00C6W1-3Y for linux-arm-kernel@lists.infradead.org; Wed, 26 Jan 2022 15:03:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3973B1FB; Wed, 26 Jan 2022 07:02:54 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 523AE3F793; Wed, 26 Jan 2022 07:02:53 -0800 (PST) Date: Wed, 26 Jan 2022 15:02:50 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, jaxson.han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: Re: [bootwrapper PATCH v3 01/15] aarch64: correct ZCR_EL3.LEN initialization Message-ID: <20220126150250.2dd88556@donnerap.cambridge.arm.com> In-Reply-To: <20220125150057.3936090-2-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> <20220125150057.3936090-2-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_070259_253653_9A56BF88 X-CRM114-Status: GOOD ( 19.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 25 Jan 2022 15:00:43 +0000 Mark Rutland wrote: > The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are > RAZ/WI, likely so that in future these can be used to extend LEN without > complicating the probing of the maximum available vector length. > > Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN > field and the RAZ/WI bits. > > To match the architecture as documented, reduce this down to 0xf, only > covering the bits currently allocated to the LEN field. We can extend > this in future if the LEN field is widened. > > As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is > used as a value rather than as a bit mask. > > Signed-off-by: Mark Rutland > Cc: Andre Przywara > Cc: Mark Brown Looks good to me: Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/aarch64/boot.S | 2 +- > arch/aarch64/include/asm/cpu.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 72c6b79..ee9ddaa 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -123,7 +123,7 @@ ASM_FUNC(_start) > msr cptr_el3, x0 > isb > > - mov x0, #ZCR_EL3_LEN_MASK // SVE: Enable full vector len > + mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len > msr ZCR_EL3, x0 // for EL2. > > 1: > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 63eb1c3..e3269b8 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -30,7 +30,7 @@ > #define CPTR_EL3_EZ (1 << 8) > > #define ZCR_EL3 s3_6_c1_c2_0 > -#define ZCR_EL3_LEN_MASK 0x1ff > +#define ZCR_EL3_LEN_MAX 0xf > > #define SCTLR_EL1_CP15BEN (1 << 5) > #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel