From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03D7AC28CF5 for ; Wed, 26 Jan 2022 17:23:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TLORrvT5mkP6W+ROT28v1s7LBgi+CcKxSB+dJu4G7u8=; b=dj3i1PTNMqUJhD r+iOuZYpLjx3cOLzX+YmbNLUZjh5A8ATUmQf03lU5tIs0DRl/+ge95jxKj8otHxz2jpM7/fwDI791 2Kk731J4td8MQxsr1eS7KeYzQpWW6yeevLxQ+ZgpIyDXzMMJgv94XXXJm21UEItZoj1Pi3Epkq1Bp N3HXge1PgsIMMIoLpPx+1ECksDYlxCFHuBWSrewJ1WOwMFSfR9xr7jHHpwmJrRFuRIDNKgmTeD5Fl Pfpn6BwAEvM1nYgjuvPahgF7b17JNE32KLYUNhCbWzfWj9l7m1Cl6Ao0aYOH2lrmpGVQXpQ5i8BwY nxdLxzz9zSItKWqtwGbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nClzx-00CxyD-W8; Wed, 26 Jan 2022 17:22:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nClH3-00Cg4O-AF for linux-arm-kernel@lists.infradead.org; Wed, 26 Jan 2022 16:35:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FDCBD6E; Wed, 26 Jan 2022 08:35:56 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F4D83F766; Wed, 26 Jan 2022 08:35:55 -0800 (PST) Date: Wed, 26 Jan 2022 16:35:53 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, jaxson.han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: Re: [bootwrapper PATCH v3 08/15] aarch64: initialize SCTLR_ELx for the boot-wrapper Message-ID: <20220126163553.1c6ba46e@donnerap.cambridge.arm.com> In-Reply-To: <20220125150057.3936090-9-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> <20220125150057.3936090-9-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_083557_528086_A4F2DE88 X-CRM114-Status: GOOD ( 23.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 25 Jan 2022 15:00:50 +0000 Mark Rutland wrote: Hi, > The SCTLR_ELx registers contain fields which are UNKNOWN or > IMPLEMENTATION DEFINED out of reset. This includes SCTLR_ELx.EE, which > defines the endianness of memory accesses (e.g. reads from literal > pools). Due to this, portions of boot-wrapper code are not guaranteed > to work correctly. > > Rework the startup code to explicitly initialize SCTLR_ELx for the > exception level the boot-wrapper was entered at. When entered at EL2 > it's necessary to first initialise HCR_EL2.E2H as this affects the RESx > behaviour of bits in SCTLR_EL2, and also aliases SCTLR_EL1 to SCTLR_EL2, > which would break the initialization performed in jump_kernel. > > As we plan to eventually support the highest implemented EL being any of > EL3/EL2/EL1, code is added to handle all of these exception levels, even > though we do not currently support starting at EL1. > > We'll initialize other registers in subsequent patches. While I still would like to have seen bit 7 cleared and bit 5 set in SCTLR_EL1, that is admittedly debatable, and any EL1 user should set that for their EL0 themselves. The rest is fine, so: > Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/aarch64/boot.S | 74 +++++++++++++++++++++++++++------- > arch/aarch64/include/asm/cpu.h | 30 +++++++++++++- > 2 files changed, 88 insertions(+), 16 deletions(-) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index d682ba5..204c199 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -26,26 +26,26 @@ > * PSCI is not supported when entered in this exception level. > */ > ASM_FUNC(_start) > - cpuid x0, x1 > - bl find_logical_id > - cmp x0, #MPIDR_INVALID > - beq err_invalid_id > - bl setup_stack > - > - /* > - * EL3 initialisation > - */ > mrs x0, CurrentEL > cmp x0, #CURRENTEL_EL3 > - b.eq 1f > + b.eq reset_at_el3 > + cmp x0, #CURRENTEL_EL2 > + b.eq reset_at_el2 > + cmp x0, #CURRENTEL_EL1 > + b.eq reset_at_el1 > > - mov w0, #1 > - ldr x1, =flag_no_el3 > - str w0, [x1] > + /* Booting at EL0 is not supported */ > + b . > > - b start_no_el3 > + /* > + * EL3 initialisation > + */ > +reset_at_el3: > + mov_64 x0, SCTLR_EL3_RESET > + msr sctlr_el3, x0 > + isb > > -1: mov x0, #0x30 // RES1 > + mov x0, #0x30 // RES1 > orr x0, x0, #(1 << 0) // Non-secure EL1 > orr x0, x0, #(1 << 8) // HVC enable > > @@ -143,10 +143,54 @@ ASM_FUNC(_start) > ldr x0, =COUNTER_FREQ > msr cntfrq_el0, x0 > > + cpuid x0, x1 > + bl find_logical_id > + cmp x0, #MPIDR_INVALID > + b.eq err_invalid_id > + bl setup_stack > + > bl gic_secure_init > > b start_el3 > > + /* > + * EL2 initialization > + */ > +reset_at_el2: > + // Ensure E2H is not in use > + mov_64 x0, HCR_EL2_RESET > + msr hcr_el2, x0 > + isb > + > + mov_64 x0, SCTLR_EL2_RESET > + msr sctlr_el2, x0 > + isb > + > + b reset_no_el3 > + > + /* > + * EL1 initialization > + */ > +reset_at_el1: > + mov_64 x0, SCTLR_EL1_RESET > + msr sctlr_el1, x0 > + isb > + > + b reset_no_el3 > + > +reset_no_el3: > + cpuid x0, x1 > + bl find_logical_id > + cmp x0, #MPIDR_INVALID > + b.eq err_invalid_id > + bl setup_stack > + > + mov w0, #1 > + ldr x1, =flag_no_el3 > + str w0, [x1] > + > + b start_no_el3 > + > err_invalid_id: > b . > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 341a545..0a4085b 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -14,6 +14,35 @@ > #define MPIDR_ID_BITS 0xff00ffffff > > #define CURRENTEL_EL3 (3 << 2) > +#define CURRENTEL_EL2 (2 << 2) > +#define CURRENTEL_EL1 (1 << 2) > + > +/* > + * RES1 bit definitions definitions as of ARM DDI 0487G.b > + * > + * These includes bits which are RES1 in some configurations. > + */ > +#define SCTLR_EL3_RES1 \ > + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ > + BIT(11) | BIT(5) | BIT(4)) > + > +#define SCTLR_EL2_RES1 \ > + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ > + BIT(16) | BIT(11) | BIT(5) | BIT(4)) > + > +#define SCTLR_EL1_RES1 \ > + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ > + BIT(8) | BIT(7) | BIT(4)) > + > +#define HCR_EL2_RES1 (BIT(1)) > + > +/* > + * Initial register values required for the boot-wrapper to run out-of-reset. > + */ > +#define SCTLR_EL3_RESET SCTLR_EL3_RES1 > +#define SCTLR_EL2_RESET SCTLR_EL2_RES1 > +#define SCTLR_EL1_RESET SCTLR_EL1_RES1 > +#define HCR_EL2_RESET HCR_EL2_RES1 > > #define ID_AA64PFR0_EL1_GIC BITS(27, 24) > > @@ -43,7 +72,6 @@ > #define ZCR_EL3_LEN_MAX 0xf > > #define SCTLR_EL1_CP15BEN (1 << 5) > -#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) > > #ifdef KERNEL_32 > /* _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel