linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Ard Biesheuvel <ardb@kernel.org>
To: linux@armlinux.org.uk
Cc: linux-arm-kernel@lists.infradead.org,
	Ard Biesheuvel <ardb@kernel.org>,
	Steven Rostedt <rostedt@goodmis.org>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Cristian Marussi <cristian.marussi@arm.com>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Masami Hiramatsu <mhiramat@kernel.org>
Subject: [PATCH v2 11/12] ARM: cacheflush: avoid clobbering the frame pointer in Thumb2 mode
Date: Mon, 31 Jan 2022 18:03:46 +0100	[thread overview]
Message-ID: <20220131170347.381551-12-ardb@kernel.org> (raw)
In-Reply-To: <20220131170347.381551-1-ardb@kernel.org>

Thumb2 uses R7 rather than R11 as the frame pointer, and even if we
rarely use a frame pointer to begin with when building in Thumb2 mode,
there are cases where it is required by the compiler (Clang when
inserting profiling hooks via -pg)

So let's preserve whichever register is considered the frame pointer
depending on whether we are building for ARM or Thumb2, rather than
preserving/restoring R11 explicitly.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/arm/include/asm/cacheflush.h  | 7 ++++---
 arch/arm/mach-exynos/mcpm-exynos.c | 7 ++++---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index e68fb879e4f9..5c4c49086ac6 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -12,6 +12,7 @@
 #include <asm/glue-cache.h>
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
+#include <asm/opcodes.h>
 #include <asm/outercache.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
@@ -454,7 +455,7 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
 #define v7_exit_coherency_flush(level) \
 	asm volatile( \
 	".arch	armv7-a \n\t" \
-	"stmfd	sp!, {fp, ip} \n\t" \
+	"stmfd	sp!, {" FPREG_PRESERVE ", ip} \n\t" \
 	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR \n\t" \
 	"bic	r0, r0, #"__stringify(CR_C)" \n\t" \
 	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR \n\t" \
@@ -465,8 +466,8 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
 	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR \n\t" \
 	"isb	\n\t" \
 	"dsb	\n\t" \
-	"ldmfd	sp!, {fp, ip}" \
-	: : : "r0","r1","r2","r3","r4","r5","r6","r7", \
+	"ldmfd	sp!, {" FPREG_PRESERVE ", ip}" \
+	: : : "r0","r1","r2","r3","r4","r5","r6", FPREG_CLOBBER, \
 	      "r9","r10","lr","memory" )
 
 void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index cd861c57d5ad..0cebc008d877 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -14,6 +14,7 @@
 #include <asm/cputype.h>
 #include <asm/cp15.h>
 #include <asm/mcpm.h>
+#include <asm/opcodes.h>
 #include <asm/smp_plat.h>
 
 #include "common.h"
@@ -35,7 +36,7 @@ static bool secure_firmware __ro_after_init;
  */
 #define exynos_v7_exit_coherency_flush(level) \
 	asm volatile( \
-	"stmfd	sp!, {fp, ip}\n\t"\
+	"stmfd	sp!, {" FPREG_PRESERVE ", ip} \n\t" \
 	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
 	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
 	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
@@ -50,10 +51,10 @@ static bool secure_firmware __ro_after_init;
 	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
 	"isb\n\t" \
 	"dsb\n\t" \
-	"ldmfd	sp!, {fp, ip}" \
+	"ldmfd	sp!, {" FPREG_PRESERVE ", ip}" \
 	: \
 	: "Ir" (pmu_base_addr + S5P_INFORM0) \
-	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", FPREG_CLOBBER, \
 	  "r9", "r10", "lr", "memory")
 
 static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-01-31 17:25 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-31 17:03 [PATCH v2 00/12] ARM: ftrace fixes and cleanups Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 01/12] ARM: ftrace: ensure that ADR take Thumb bit into account Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 02/12] ARM: ftrace: use ADD not POP to counter PUSH at entry Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 03/12] ARM: ftrace: use trampolines to keep .init.text in branching range Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 04/12] ARM: ftrace: avoid redundant loads or clobbering IP Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 05/12] ARM: ftrace: avoid unnecessary literal loads Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 06/12] ARM: ftrace: enable HAVE_FUNCTION_GRAPH_FP_TEST Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 07/12] ARM: unwind: track location of LR value in stack frame Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 08/12] ARM: ftrace: enable the graph tracer with the EABI unwinder Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 09/12] ARM: kprobes: treat R7 as the frame pointer register in Thumb2 builds Ard Biesheuvel
2022-01-31 18:31   ` Nick Desaulniers
2022-02-01  7:42     ` Ard Biesheuvel
2022-02-01 13:18   ` Masami Hiramatsu
2022-02-01 14:05     ` Ard Biesheuvel
2022-02-02  6:10       ` Masami Hiramatsu
2022-02-02  8:00         ` Ard Biesheuvel
2022-01-31 17:03 ` [PATCH v2 10/12] drivers/firmware/scmi: disable ftrace for Clang " Ard Biesheuvel
2022-01-31 18:37   ` Nick Desaulniers
2022-02-01  8:12     ` Ard Biesheuvel
2022-01-31 22:04   ` Sudeep Holla
2022-01-31 17:03 ` Ard Biesheuvel [this message]
2022-01-31 18:40   ` [PATCH v2 11/12] ARM: cacheflush: avoid clobbering the frame pointer in Thumb2 mode Nick Desaulniers
2022-01-31 17:03 ` [PATCH v2 12/12] Revert "ARM: 9144/1: forbid ftrace with clang and thumb2_kernel" Ard Biesheuvel
2022-01-31 18:42   ` Nick Desaulniers
2022-01-31 17:21 ` [PATCH v2 00/12] ARM: ftrace fixes and cleanups Steven Rostedt

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220131170347.381551-12-ardb@kernel.org \
    --to=ardb@kernel.org \
    --cc=arnd@arndb.de \
    --cc=cristian.marussi@arm.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux@armlinux.org.uk \
    --cc=mhiramat@kernel.org \
    --cc=nathan@kernel.org \
    --cc=ndesaulniers@google.com \
    --cc=rostedt@goodmis.org \
    --cc=sudeep.holla@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).