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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id s14sm23347006pfk.174.2022.02.01.09.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 09:00:25 -0800 (PST) Date: Tue, 1 Feb 2022 10:00:23 -0700 From: Mathieu Poirier To: James Clark Cc: coresight@lists.linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/1] coresight: Fix TRCCONFIGR.QE sysfs interface Message-ID: <20220201170023.GA2490199@p14s> References: <20220120113047.2839622-1-james.clark@arm.com> <20220120113047.2839622-2-james.clark@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220120113047.2839622-2-james.clark@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220201_090028_727725_8FA6925C X-CRM114-Status: GOOD ( 27.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 20, 2022 at 11:30:47AM +0000, James Clark wrote: > It's impossible to program a valid value for TRCCONFIGR.QE > when TRCIDR0.QSUPP==0b10. In that case the following is true: > > Q element support is implemented, and only supports Q elements without > instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11. > > Currently the low bit of QSUPP is checked to see if the low bit of QE can > be written to, but as you can see when QSUPP==0b10 the low bit is cleared > making it impossible to ever write the only valid value of 0b11 to QE. > 0b10 would be written instead, which is a reserved QE value even for all > values of QSUPP. > > The fix is to allow writing the low bit of QE for any non zero value of > QSUPP. > > This change also ensures that the low bit is always set, even when the > user attempts to only set the high bit. > > Signed-off-by: James Clark > Reviewed-by: Mike Leach > --- > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index a0640fa5c55b..57e94424a8d6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, > mode = ETM_MODE_QELEM(config->mode); > /* start by clearing QE bits */ > config->cfg &= ~(BIT(13) | BIT(14)); > - /* if supported, Q elements with instruction counts are enabled */ > - if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) > + /* > + * if supported, Q elements with instruction counts are enabled. > + * Always set the low bit for any requested mode. Valid combos are > + * 0b00, 0b01 and 0b11. > + */ > + if (mode && drvdata->q_support) > config->cfg |= BIT(13); Interesting brain gymnastic - applied. Thanks, Mathieu > /* > * if supported, Q elements with and without instruction > -- > 2.28.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel