From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4EADC433F5 for ; Thu, 3 Feb 2022 12:14:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CJ67gt+ejRY5YqfuJQzOnHcrAsstHQGTB93G2TtbfIA=; b=tzqKMqHkzufnKc NfGMJpq4WhYh4UCOl6Oz3JG11kiZ9yMa+n37I8bVm+T/wIR0PzFd9sCpGoT5Aj4xS0+p7GV/xXXVe XdKAxmh4jEXkcoDLbgjVL+yNCwb6iLuYLTsQ7oyvlG7nu8CxlYnFFw3SMdAcSiodgUQ2ja3xaKE2C Cv2DOSQgO2oyeVTyxskTgAMPpyk1cZ7Zp/hjyeIqalgt9UJiQKSNRbSfj06/Anc9NWdTDrrqPlzhW dhG76HQPty+3fBGbseKg/QPA5tx9VZgZQuKckw3pPOz46t76n88Vr2fFGRmdJ9/zUIzfOKJ5tMoNX 9uDQr8pEVrmZhYbSSQwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFayz-001A2u-R4; Thu, 03 Feb 2022 12:13:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFasp-00179E-9R for linux-arm-kernel@lists.infradead.org; Thu, 03 Feb 2022 12:06:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A764E11D4; Thu, 3 Feb 2022 04:06:38 -0800 (PST) Received: from e121896.arm.com (unknown [10.57.13.234]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2C2CE3F774; Thu, 3 Feb 2022 04:06:37 -0800 (PST) From: James Clark To: suzuki.poulose@arm.com, mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/15] coresight: Make ETM4x TRCACATRn register accesses consistent with sysreg.h Date: Thu, 3 Feb 2022 12:05:59 +0000 Message-Id: <20220203120604.128396-12-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220203120604.128396-1-james.clark@arm.com> References: <20220203120604.128396-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220203_040639_466388_072B0765 X-CRM114-Status: GOOD ( 12.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-sysfs.c | 43 ++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++-- 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 87e52f685f05..51f6e13e3b29 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -22,7 +22,7 @@ static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude) * TRCACATRn.TYPE bit[1:0]: type of comparison * the trace unit performs */ - if (BMVAL(config->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) { + if (REG_VAL(config->addr_acc[idx], TRCACATRn_TYPE) == TRCACATRn_TYPE_ADDR) { if (idx % 2 != 0) return -EINVAL; @@ -863,11 +863,11 @@ static ssize_t addr_instdatatype_show(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; - val = BMVAL(config->addr_acc[idx], 0, 1); + val = REG_VAL(config->addr_acc[idx], TRCACATRn_TYPE); len = scnprintf(buf, PAGE_SIZE, "%s\n", - val == ETM_INSTR_ADDR ? "instr" : - (val == ETM_DATA_LOAD_ADDR ? "data_load" : - (val == ETM_DATA_STORE_ADDR ? "data_store" : + val == TRCACATRn_TYPE_ADDR ? "instr" : + (val == TRCACATRn_TYPE_DATA_LOAD_ADDR ? "data_load" : + (val == TRCACATRn_TYPE_DATA_STORE_ADDR ? "data_store" : "data_load_store"))); spin_unlock(&drvdata->spinlock); return len; @@ -891,7 +891,7 @@ static ssize_t addr_instdatatype_store(struct device *dev, idx = config->addr_idx; if (!strcmp(str, "instr")) /* TYPE, bits[1:0] */ - config->addr_acc[idx] &= ~(BIT(0) | BIT(1)); + config->addr_acc[idx] &= ~(TRCACATRn_TYPE_MASK << TRCACATRn_TYPE_SHIFT); spin_unlock(&drvdata->spinlock); return size; @@ -1149,7 +1149,7 @@ static ssize_t addr_ctxtype_show(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; /* CONTEXTTYPE, bits[3:2] */ - val = BMVAL(config->addr_acc[idx], 2, 3); + val = REG_VAL(config->addr_acc[idx], TRCACATRn_CONTEXTTYPE); len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" : (val == ETM_CTX_CTXID ? "ctxid" : (val == ETM_CTX_VMID ? "vmid" : "all"))); @@ -1175,18 +1175,19 @@ static ssize_t addr_ctxtype_store(struct device *dev, idx = config->addr_idx; if (!strcmp(str, "none")) /* start by clearing context type bits */ - config->addr_acc[idx] &= ~(BIT(2) | BIT(3)); + config->addr_acc[idx] &= ~(TRCACATRn_CONTEXTTYPE_MASK << + TRCACATRn_CONTEXTTYPE_SHIFT); else if (!strcmp(str, "ctxid")) { /* 0b01 The trace unit performs a Context ID */ if (drvdata->numcidc) { - config->addr_acc[idx] |= BIT(2); - config->addr_acc[idx] &= ~BIT(3); + config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID; + config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "vmid")) { /* 0b10 The trace unit performs a VMID */ if (drvdata->numvmidc) { - config->addr_acc[idx] &= ~BIT(2); - config->addr_acc[idx] |= BIT(3); + config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_CTXID; + config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "all")) { /* @@ -1194,9 +1195,9 @@ static ssize_t addr_ctxtype_store(struct device *dev, * comparison and a VMID */ if (drvdata->numcidc) - config->addr_acc[idx] |= BIT(2); + config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID; if (drvdata->numvmidc) - config->addr_acc[idx] |= BIT(3); + config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID; } spin_unlock(&drvdata->spinlock); return size; @@ -1215,7 +1216,7 @@ static ssize_t addr_context_show(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; /* context ID comparator bits[6:4] */ - val = BMVAL(config->addr_acc[idx], 4, 6); + val = REG_VAL(config->addr_acc[idx], TRCACATRn_CONTEXT); spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1240,8 +1241,8 @@ static ssize_t addr_context_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; /* clear context ID comparator bits[6:4] */ - config->addr_acc[idx] &= ~(BIT(4) | BIT(5) | BIT(6)); - config->addr_acc[idx] |= (val << 4); + config->addr_acc[idx] &= ~(TRCACATRn_CONTEXT_MASK << TRCACATRn_CONTEXT_SHIFT); + config->addr_acc[idx] |= (val << TRCACATRn_CONTEXT_SHIFT); spin_unlock(&drvdata->spinlock); return size; } @@ -1258,7 +1259,7 @@ static ssize_t addr_exlevel_s_ns_show(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; - val = BMVAL(config->addr_acc[idx], 8, 14); + val = REG_VAL(config->addr_acc[idx], TRCACATRn_EXLEVEL); spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1275,14 +1276,14 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; - if (val & ~((GENMASK(14, 8) >> 8))) + if (val & ~TRCACATRn_EXLEVEL_MASK) return -EINVAL; spin_lock(&drvdata->spinlock); idx = config->addr_idx; /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ - config->addr_acc[idx] &= ~(GENMASK(14, 8)); - config->addr_acc[idx] |= (val << 8); + config->addr_acc[idx] &= ~(TRCACATRn_EXLEVEL_MASK << TRCACATRn_EXLEVEL_SHIFT); + config->addr_acc[idx] |= (val << TRCACATRn_EXLEVEL_SHIFT); spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 02afce9dcf6b..5701d970d81a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -236,6 +236,16 @@ #define TRCVICTLR_EXLEVEL_NS_SHIFT 20 #define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(2, 0) +#define TRCACATRn_TYPE_SHIFT 0 +#define TRCACATRn_TYPE_MASK GENMASK(1, 0) +#define TRCACATRn_CONTEXTTYPE_SHIFT 2 +#define TRCACATRn_CONTEXTTYPE_MASK GENMASK(1, 0) +#define TRCACATRn_CONTEXTTYPE_CTXID BIT(2) +#define TRCACATRn_CONTEXTTYPE_VMID BIT(3) +#define TRCACATRn_CONTEXT_SHIFT 4 +#define TRCACATRn_CONTEXT_MASK GENMASK(2, 0) +#define TRCACATRn_EXLEVEL_SHIFT 8 +#define TRCACATRn_EXLEVEL_MASK GENMASK(6, 0) /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions @@ -1078,10 +1088,10 @@ struct etmv4_drvdata { /* Address comparator access types */ enum etm_addr_acctype { - ETM_INSTR_ADDR, - ETM_DATA_LOAD_ADDR, - ETM_DATA_STORE_ADDR, - ETM_DATA_LOAD_STORE_ADDR, + TRCACATRn_TYPE_ADDR, + TRCACATRn_TYPE_DATA_LOAD_ADDR, + TRCACATRn_TYPE_DATA_STORE_ADDR, + TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR, }; /* Address comparator context types */ -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel