From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AF5AC433EF for ; Sat, 5 Feb 2022 00:09:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BN18ycBcl66X74X97qSHrvQIUd7vw/9Bkl5V+66Dxks=; b=1kmg9FWaLexTnb /rQ1v2wPhpTaD8PhayXdFBNZuTBuv582zr5eTpqPnsZeSczX+R8XiSbARm8mZalD1lfdlAtWIWAcX v6sx3pYJboc9WBndckXIwe+kbSJhCT9Rlyq48rm+Ll6RI39U9amcEhCWZO8udc+CpDAcB+QBCiHQE RS3hNE9SPrbAuVaoPYGqBOmvOR0A47eCgLl+pyUL4mRf+KfZJ32BMeoYdQhnlzo0VSR+DNhYMPfa3 VOjeTdLwpiAu0TN/2LZUQzF9h9HiRWEwilAw/iQX9SbW7jXiOxHWUREvzoFFesUfaOcQMT5SCb/KG ITTUynxmgLPG9HpBwugQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nG8c5-005paP-In; Sat, 05 Feb 2022 00:07:37 +0000 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nG8c2-005pZK-AE for linux-arm-kernel@lists.infradead.org; Sat, 05 Feb 2022 00:07:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1644019654; x=1675555654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5wfmLOODIoBBqoFFpobkufQhEkHn9jh4Dhowg0sJqm0=; b=wGvtx/+DLangzpDP6reobZQQhwPcp5ZzQtZZmjm0w2Yei0PojzE1NGEL 8WilnmSO5taXkzhAKkEaprozfEScdQlmV3gSeL6f9tLCauLn5orZKitE0 64xiaudr1nYC5nQjBBW9Qc8PMME6l2dpPkQJUasoSSkbsdlqZBpg0S5ZJ M=; X-IronPort-AV: E=Sophos;i="5.88,344,1635206400"; d="scan'208";a="175745942" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-pdx-2b-22c2b493.us-west-2.amazon.com) ([10.43.8.6]) by smtp-border-fw-6001.iad6.amazon.com with ESMTP; 05 Feb 2022 00:07:29 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2b-22c2b493.us-west-2.amazon.com (Postfix) with ESMTPS id D986741560; Sat, 5 Feb 2022 00:07:24 +0000 (UTC) Received: from EX13D02UWC001.ant.amazon.com (10.43.162.243) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.28; Sat, 5 Feb 2022 00:07:23 +0000 Received: from EX13MTAUEE002.ant.amazon.com (10.43.62.24) by EX13D02UWC001.ant.amazon.com (10.43.162.243) with Microsoft SMTP Server (TLS) id 15.0.1497.28; Sat, 5 Feb 2022 00:07:23 +0000 Received: from dev-dsk-alisaidi-i31e-9f3421fe.us-east-1.amazon.com (10.200.138.153) by mail-relay.amazon.com (10.43.62.224) with Microsoft SMTP Server id 15.0.1497.28 via Frontend Transport; Sat, 5 Feb 2022 00:07:22 +0000 Received: by dev-dsk-alisaidi-i31e-9f3421fe.us-east-1.amazon.com (Postfix, from userid 5131138) id B438021B50; Sat, 5 Feb 2022 00:07:22 +0000 (UTC) From: Ali Saidi To: CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH] perf arm-spe: Use SPE data source for neoverse cores Date: Sat, 5 Feb 2022 00:07:19 +0000 Message-ID: <20220205000719.19986-1-alisaidi@amazon.com> X-Mailer: git-send-email 2.24.4.AMZN In-Reply-To: <20220203091934.GA2013381@leoy-ThinkPad-X240s> References: <20220203091934.GA2013381@leoy-ThinkPad-X240s> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220204_160734_538549_78C180C4 X-CRM114-Status: GOOD ( 27.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Leo, On 2/3/22, 3:20 AM, "Leo Yan" wrote: >[...] >> >> >> + data_src.mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; >> >> > >> >> >This one also adds PERF_MEM_LVL_HIT even though the check of "if (record->type & ARM_SPE_LLC_MISS)" >> >> >hasn't happened yet. Maybe some comments would make it a bit clearer, but at the moment it's >> >> >not obvious how the result is derived because there are some things that don't add up like >> >> >ARM_SPE_LLC_MISS == PERF_MEM_LVL_HIT. >> >> >> >> Assuming the above is correct, my reading of the existing code that creates the >> >> c2c output is that when an access is marked as an LLC hit, that doesn't >> >> necessarily mean that the data was present in the LLC. I don't see how it could >> >> given that LLC_HIT + HITM means the line was dirty in another CPUs cache, and so >> >> LLC_HIT + HITM seems to mean that it was a hit in the LLC snoop filter and >> >> required a different core to provide the line. This and the above certainly >> >> deserve a comment as to why the miss is being attributed in this way if it's >> >> otherwise acceptable. >> > >> >As James pointed out, this might introduce confusion. I am wanderding >> >if we can extract two functions for synthesizing the data source, one is >> >for Neoverse platform and another is for generic purpose (which >> >without data source packets), below code is to demonstrate the basic >> >idea. >> >> The code below is cleaner, and I'm happy to rework the patches in this way, but >> I think the question still remains about unifying behavior of the tool. If we >> mark something with a data source of ARM_SPE_NV_PEER_CORE as at L1 hit + HITM >> certainly c2c won't show the correct thing today, but i think it also hides the >> intent. The line in question missed the L1, L2, and got to the LLC where we did >> find a record that it was in another cores cache (L1 or L2). Looking at the way >> that c2c works today, it seems like marking this as a hit in the LLC snoop >> filter is the best way to unify behaviors among architectures? > >Thanks a lot for pointing out this. I looked into the code and >compared the memory trace data from x86, I found the HITM tag is always >sticking to LLC from x86's memory events. This would be the main reason >why current code in perf is only support HITM for LLC. > >I don't think it's a good way to always mark LLC snoop, even it's a >snooping operation in L1 or L2 cache on Arm64 platforms; this would >introduce confusion for users when using Arm SPE for profiling. > >Alternatively, we can support HITM tag for L1/L2 cache levels in perf, >this can allow us to match memory topology on Arm64 arch, and it should >not introduce any regression on x86 arch. > >Could you confirm if below code can fix the issue or not? Yes, that should do it. Want me to repsin this with the changes we discussed? Ali _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel